Showing papers on "Carry-lookahead adder published in 1986"

Optimally partitioned regenerative carry lookahead adder

Abstract: An improved scheme for generating a carry lookahead is described. An irregular grouping, wherein large bit groups are used in the middle and shorter bit groups are used at the ends, provides for a reduction in carry propagation delay.

Parallel multiplier circuit

Abstract: The multiplier data (Y) are coded by coders on the basis of the modified Booth algorithm and output control signals in accordance with the coding result. Basic cells (C) are arranged in an arrangement or array of n stages. Each basic cell (C) adds the data corresponding to the multiplicand data (X) to the outputs of the basic cells (C) of the preceding (front) stage in dependence on these control signals. For the relevant lower-order (n-1) stages from the n stages, two-bit carry lookahead adders (CLA1-CLA3) are provided, each of which picks up the outputs of the basic cell (Ci, 1) of the least-significant bit of the same stage and of the second basic cell (Ci, 2) after the least-signficant bit, the complement signal from a complement signal generating unit (EC1-EC4) and a carry signal of the carry lookahead adder (CLAi-1) of the preceding stage and each of which generates a carry signal with virtually the same delay time as that of that basic cell in order to utilise the highest operating speed of the basic cells (C) arranged in a matrix form. Furthermore, each carry lookahead adder (CLA1-CLA3) derives the data of the relevant two bits of the end product. An upper adder (9) picks up the outputs of the basic cells (C4, k) of the nth stage and the carry signal of the carry lookahead adder (CLA3) of the (n-1)th stage, adds the inputs and derives the data of the higher-order bits ... Original abstract incomplete.