Showing papers on "Carry-lookahead adder published in 1988"
Patent•
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06 Jul 1988
TL;DR: The binary coded decimal adder circuit for adding two BCD encoded operands and for producing a binary coded encoded sum includes a bank of parallel full adder circuits as a first stage which generate an intermediate sum vector and an intermediate carry vector from the sum of the operands as mentioned in this paper.
Abstract: The binary coded decimal (BCD) adder circuit for adding two BCD encoded operands and for producing a BCD encoded sum includes a bank of parallel full adder circuits as a first stage which generate an intermediate sum vector and an intermediate carry vector from the sum of the operands and a precorrection factor. A second stage of the BCD adder circuit includes carry lookahead adder circuitry receiving as inputs the intermediate sum vector and the intermediate carry vector and producing a propagate vector and a final carry vector. The third stage of the BCD adder circuit conditionally modifies the propagate vector to form the BCD encoded sum according to bits of the intermediate carry vector and the final carry vector as inputs.
23 citations
Patent•
16 Dec 1988TL;DR: In this article, a metal-oxide-semiconductor (MOS) partitioned carry lookahead adder fabricated from a plurality of four bit slice blocks is described, where the blocks are organized into groups of optimum size with logic in each group to generate a group propagate signal.
Abstract: A metal-oxide-semiconductor (MOS) partitioned carry lookahead adder fabricated from a plurality of four bit slice blocks. Each block provides four sum signals and provides a block carry signal. The blocks are organized into groups of optimum size with logic in each group to generate a group propagate signals. Each block has a block carry line with a single transistor connected between the input and output terminals of the block. The blocks employ an intermediate carry circuit for computing sums in place of full adders. In addition, there is a main carry line with transistors controlled by the group propagate signals for a 32 bit adder, the maximum pass gate delay in the carry chain is three pass gates.
16 citations
Patent•
16 Dec 1988TL;DR: In this paper, a metal-oxide-semiconductor (MOS) partitioned carry lookahead adder fabricated from a plurality of four-bit slice blocks is described, where each block provides four sum signals and provides a block carry signal.
Abstract: An metal-oxide-semiconductor (MOS) partitioned carry lookahead adder fabricated from a plurality of four bit slice blocks. Each block provides four sum signals and provides a block carry signal. The blocks are organized into groups of optimum size with logic in each group to generate a group propagate signals. Each block has a block carry line with a single transistor connected between the input and output terminals of the block. The blocks employ an intermediate carry circuit for computing sums in place of full adders. In addition, there is a main carry line with transistors controlled by the group propagate signals. For a 32 bit adder, the maximum pass gate delay in the carry chain is three pass gates.
15 citations