Showing papers on "Carry-lookahead adder published in 1990"
24 Jun 1990
TL;DR: A heuristic for speeding up combinational logic by decreasing the logic depth, at the expense of a minimal increase in circuit size is described, capable of reproducing or even beating several classic global optimizations.
Abstract: This paper describes a heuristic for speeding up combinational logic by decreasing the logic depth, at the expense of a minimal increase in circuit size. The heuristic iteratively speeds up sections of the critical path by the use of Shannon factorization on the late input. This procedure is empirically found to be capable of reproducing or even beating several classic global optimizations: a chain of an associative operator is transformed into a tree, a ripple prefix circuit into a parallel prefix circuit, and a ripple-carry adder into a slightly smaller and faster circuit than the carry-lookahead adder.
70 citations
07 Jun 1990
TL;DR: A 54-b×54-b multiplier fabricated in double metal 0.5-μm CMOS technology is described, intended for double-precision floating-point data processing based on IEEE standards up to a clock range of 100 MHz.
Abstract: A 54-bt54-b multiplier fabricated in double metal 0.5-mm CMOS technology is described. A 10-ns multiplication time has been achieved by employing a 4-2 compressor, a carry select adder, and a carry lookahead adder. The 54-bt54-b full array is adopted to complete the multiplication within one latency. This multiplier is intended for double-precision floating-point data processing based on IEEE standards up to a clock range of 100 MHz. The multiplier has integrated 81600 transistors in an active area of 3.62 mmt3.45 mm
6 citations
05 Nov 1990
TL;DR: Simulation results show that the CLA structures in wide use can be improved by varying the block sizes and the number of levels within each adder.
Abstract: The delay characteristics of carrylookahead (CLA) adders are examined with respect to a delay model that accounts for fan-in and fanout dependencies. Though CLA structures are considered among the fastest topologies for performing addition, they have also been characterized as providing marginal speed improvement for the amount of hardware invested. This analysis shows that this inefficiency can be explained by the suboptimal nature of common CLA implementations. Simulation results show that the CLA structures in wide use can be improved by varying the block sizes and the number of levels within each adder. Examples of optimal CLA structures are given and heuristic methods for finding these structures are presented.
6 citations
05 Nov 1990
TL;DR: This paper describes the design of a 16 x 16 Wallace-trec based multiplier for signed 2’s complement numbcrs that uses a novel variable-block carry lookahead adder whose configuration is the result of a dynamic programming formulation, and is time-optimal within the class of lookahcad adders.
Abstract: This paper describes the design of a 16 x 16 Wallace-trec based multiplier for signed 2’s complement numbcrs. The multiplier uses optimization roulincs in connecting up modular carry-save adders within the Wallace tree stmcture. Furthermore, it uses a novel variable-block carry lookahead adder whose configuration is the result of a dynamic programming formulation, and is time-optimal within the class of lookahcad adders. The multiplier circuit was laid out and implemented in 1.6 U CMOS. The circuit speed is 21 ns.