Showing papers on "Carry-lookahead adder published in 1992"
TL;DR: The design of the 56-b significant adder used in the Advanced Micro Devices Am29050 microprocessor is described, which employs a novel method for combining carries which does not require the back propagation associated with carry lookahead, and is not limited to radix-2 trees.
Abstract: The design of the 56-b significant adder used in the Advanced Micro Devices Am29050 microprocessor is described. Originally implemented in a 1- mu m design role CMOS process, it evaluates 56-b sums in well under 4 ns. The adder employs a novel method for combining carries which does not require the back propagation associated with carry lookahead, and is not limited to radix-2 trees, as is the binary lookahead carry tree of R.P. Brent and H.T. Kung (1982). The adder also utilizes a hybrid carry lookahead-carry select structure which reduces the number of carriers that need to be derived in the carry lookahead tree. This approach produces a circuit well suited for CMOS implementation because of its balanced load distribution and regular layout. >
171 citations
TL;DR: In this paper, a 4-b carry lookahead adder using D-MESFETs, in 1- mu m non-self-aligned gate GaAs technology, is presented.
Abstract: Implementation of a 4-b carry lookahead adder using D-MESFETs, in 1- mu m non-self-aligned gate GaAs technology, is presented. A novel technique to improve the circuit performance using differential pass transistor logic (DPTL) is presented. Circuit structures are presented and are compared with buffered FET logic (BFL). Experimental results are provided to verify the functionality and performance of the DPTL adder. The adder occupies an area of 0.890*0.652 mm/sup 2/ (excluding the output pads) and can add up to 1 Gwords/s dissipating 242 mW of power (excluding the output drivers). >
10 citations
22 Jan 1992
TL;DR: The authors report on the speed and dynamic power dissipation of CMOS implementations of six different adders and conclude that the carry lookahead adder is the best design for word sizes between 16 and 64 bits, inclusive.
Abstract: The authors report on the speed and dynamic power dissipation of CMOS implementations of six different adders. The adders are constructed with inverters and two-to-four-input AND and OR gates. A figure of merit is presented that can be used to compare the adders based on their delay and relative dynamic power consumption. This figure of merit provides a common ground for ranking the adders in terms of their utility for WSI (wafer scale integration) applications. Extensive simulation was used to evaluate the switching characteristics, and the results are used to rank the adders in terms of speed, size, and the number of logic transitions (a measure of the dynamic power consumption for static CMOS circuits). According to the figure of merit, the carry lookahead adder is the best design for word sizes between 16 and 64 bits, inclusive. >
9 citations