Showing papers on "Carry-lookahead adder published in 1994"
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TL;DR: It is shown that by sizing transistors judiciously it is possible to gain significant speed improvements at the cost of only a slight increase in power and hence a better power-delay product.
Abstract: An approach to designing CMOS adders for both high speed and low power is presented by analyzing the performance of three types of adders - linear time adders, logN time adders and constant time adders. The representative adders used are a ripple carry adder, a blocked carry lookahead adder and several signed-digit adders, respectively. Some of the tradeoffs that are possible during the logic design of an adder to improve its power-delay product are identified. An effective way of improving the speed of a circuit is by transistor sizing which unfortunately increases power dissipation to a large extent. It is shown that by sizing transistors judiciously it is possible to gain significant speed improvements at the cost of only a slight increase in power and hence a better power-delay product. Perflex, an in-house performance driven layout generator, is used to systematically generate sized layouts. >
62 citations
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01 Jan 1994
TL;DR: The reduced area multiplier, the Wallace multiplier, and the Dadda multiplier each offer fast multiplication of signed binary numbers with the use of a large adder tree and a carry lookahead adder as mentioned in this paper.
Abstract: The reduced area multiplier, the Wallace multiplier, and the Dadda (1965) multiplier each offer fast multiplication of signed binary numbers with the use of a large adder tree and a carry lookahead adder. However, their complexity makes them undesirable for some applications. A Booth (1951) multiplier, on the other hand, offers simplicity and flexibility, by both breaking a multiplication up into pieces, and by allowing the size of the pieces to be chosen. Unfortunately, Booth multipliers become difficult to design for higher radices. The use of a fast adder tree, such as that found in a reduced area multiplier, permits straightforward design of very high radix Booth multipliers. Increasing the radix of a Booth multiplier in this manner results in large increases in speed with reasonable hardware cost. >
43 citations
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IBM1
TL;DR: In this paper, an evaluation tree circuit was proposed to reduce the number of levels of logic in a carry lookahead adder, which can also be used to form a magnitude comparator.
Abstract: An evaluation tree circuit is disclosed that produces a generate, a propagate, and a zero output for use in carry lookahead adders. Another evaluation tree circuit is disclosed that merges the generate, propagate, and zero signals from several adjacent bits or groups of bits. These evaluation trees may be used in self-resetting CMOS or CVSL circuits. They can be used to reduce the number of levels of logic in a carry lookahead adder. They can also be used to form a magnitude comparator, which is also disclosed.
9 citations
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TL;DR: A digit-serial squaring architecture based on radix-2n arithmetic is presented to carry out squaring digit serially and provides system designers with a great deal of flexibility to find the best trade-off between cost and throughput by varying the radix, the type of adder to be used and/or the number of pipelined stages.
Abstract: A digit-serial squaring architecture based on radix-2n arithmetic is presented to carry out squaring digit serially. In this paper, the conventional binary squaring algorithm is modified and a radix-2n squaring algorithm which is used to design the proposed architectures is presented. The resulting basic cell is the Digital Controlled Add/shiFt (DCAF) cell. The advantage of using radix-2n arithmetic is that it specifies the functionality of the DCAF cell only and, hence, there is no restriction on the type of adder to be used. It can be a ripple carry adder, a carry lookahead adder, a pipelined adder, or a carry-save adder. The merit of the new structure is that it provides system designers with a great deal of flexibility to find the best trade-off between cost and throughput by varying the radix, the type of adder to be used and/or the number of pipelined stages.
1 citations