Showing papers on "Carry-lookahead adder published in 1997"

Fast adders using enhanced multiple-output domino logic

Abstract: Using an enhanced multiple output domino logic (EMODL) implementation of a carry lookahead adder (CLA), sums of several consecutive bits can be built in one nFET tree with a single carry-in. Based on this result, a new sparse carry chain architecture is proposed for the CLA adder. We demonstrate the design approach using a 32-b adder, and show that only four carries are sufficient for generating all sums, with a consequent reduction in the number of stage delays. Using a 1.2-/spl mu/m CMOS technology, we verify our simulation procedures by fabrication and measurement of a 2.7 ns critical path.

Properties of the input pattern fault model

Abstract: Recent work in IC failure analysis strongly indicates the need for fault models that directly analyze the function of circuit primitives. The input pattern (IP) fault model is a functional fault model that allows for both complete and partial functional verification of every circuit module, independent of the design level. We describe the IP fault model and provide a method for analyzing IP faults using standard SSL-based fault simulators and test generation tools. The method is used to generate test sets that target the IP faults of the ISCAS85 benchmark circuits and a carry-lookahead adder. Improved IP fault coverage for the benchmarks and the adder is obtained by adding a small number of test patterns to tests that target only SSL faults. We also conducted fault simulation experiments that show IP test patterns are effective in detecting non-targeted faults such as bridging and transistor stuck-on faults. Finally, we discuss the notion of IP redundancy and show how large amounts of this redundancy exist in the benchmarks and in SSL-irredundant adder circuits.

A fast binary adder with conditional carry generation

Abstract: This paper presents a fast binary adder in static CMOS realization. While the carry derivation is similar to that in a conditional-sum adder, the proposed adder is also similar to that of a spanning tree carry lookahead adder in the sense that only selected carry bits are generated and the sum bits are produced by carry-select adders. In a 1.2 /spl mu/m static CMOS realization, the proposed adder adds two 32-bit operands in 3.28 ns. This delay is measured from the assertion of the input to the arrival of the slowest sum bit.

VLSI design of a quaternary multiplier with direct generation of partial products

Abstract: This paper presents the VLSI design of a novel quaternary multiplier with direct generation of partial products using a radix-4 redundant number system. The structure of the multiplier is so simple and regular that it is suitable for VLSI implementation. Partial products in the multiplier are generated as the corresponding value 0 to 9 and are implemented by simple CMOS current-mode circuits. To add partial products in the multiplier, we introduce a redundant multi-valued adder (RMA). The RMA can add two redundant numbers without carry propagation. The resulting numbers in the final level of additions are also redundant. We use a high speed quaternary carry-lookahead adder (QCLA) to convert a redundant number into a non-redundant number. The chip of a CMOS 4/spl times/4-digit quaternary multiplier is fabricated in cooperation with the VLSI Design and Education Center of Tokyo University, Japan. The chip and core sizes of the multiplier are 2.3/spl times/2.3 mm/sup 2/ and 1.5/spl times/1.6 mm/sup 2/, respectively with 1.5 /spl mu/m technology. The layout design of a 16/spl times/16-digit quaternary multiplier with 0.8 /spl mu/m technology is also discussed for the practical use.

Carry lookahead adder

Abstract: A high-performance carry lookahead adder (CLA) which can reduce the delay time of the whole adder by constructing a carry generator used therein with NMOS logics, thereby effecting a high-speed operation of the adder along with a lower power-consumption. The carry generator receives an exclusive-OR value P(i, i=1,2,3,4) and a logic product value G(i) of two data, and an initial carry value C(1), and performs a function of G(4)+P(4)·G(3)+P(4)·P(3)·G(2)+P(4)·P(3)·P(2)·G(1)+P(4)·P(3)·P(2)·P(1)·C(1) to output a final carry value C(5). The carry generator includes a first NMOS transistor for executing an operation of P(4)·G(3), second and third NMOS transistors for executing an operation of P(4)·P(3)·G(2), fourth to sixth NMOS transistors for executing an operation of P(4)·P(3)·P(2)·G(1), seventh to eleventh NMOS transistors for executing an operation of P(4)·P(3)·P(2)·P(1)·C(1), and twelfth to fourteenth NMOS transistors for outputting the final carry signal C(5) by an OR operation of the respective logic product terms.

A novel scheme for irregular parallel-prefix adders

Abstract: A schematic of a new 64-bit adder is presented in this paper. This adder uses the Manchester Carry Chain carry lookahead modules with spans of 4, 3, and 2. Only the first level has intermediate outputs. Unlike carry-ripple adders at the output of the Spanning Tree Carry Lookahead Adder (SPT) and the Recursive Carry-Lookahead/Carry-Select Hybrid Adder (RCS), the proposed irregular Parallel-Prefix (IPP) adder provided parallel addition at the output thus significantly reducing the number of transistors with a promising compatible speed. This will cause a considerable improvement in cost-performance. Without a carry-skip circuit, this adder also works well with a carry-in of "1" based on Brent-Kung (1982) and Tyagi's (1993) lemmas. Because the IPP adder is unidirectional, it is more appropriate for pipeline implementation. Preliminary simulation results by Mentor Graphics at static gate-level have indicated that IPP adders are faster than Tyagi's 16-bit, 32-bit and 64-bit Select-Prefix Adders. SPICE simulation at a transistor-level for a 16-bit IPP adder shows a speed of 1.756 ns. It reduces the transistor-count approximately by 21% compared to the RCS adder and by 18% compared to the SPT adder.

Combination propagate and generate carry lookahead gate

Abstract: Carry lookahead adders reduce the number of logic levels required to sum two numbers. A pure carry lookahead adder, however, requires circuits with large fan-outs and fan-ins making it impractical to build for a large number of bits. Carry lookahead tree adders use a plurality of small carry lookahead adders to build a complete adder. A binary carry lookahead adder is a typical implementation of a carry lookahead tree adder. Each stage of the binary carry lookahead adder generates a propagate output and generate output from propagate and generate inputs and calculates a carry output from a carry input. A modified generate circuit is introduced which reduces the propagation delay of the generate circuit. A modified propagate circuit is introduced that ensures the inputs to the modified propagate circuit do not create a short circuit. Additionally, a combination propagate and generate circuit is introduced which reduces the number of transistors required to implement the propagate and generate circuits. Still further, a quadrature carry lookahead tree adder is discussed and a combination propagate and generate circuit for the quadrature tree adder is presented.

Fast multiplier schemes using large parallel counters and shift switches

Abstract: We present novel fast parallel multiplier schemes. In contrast to the full adder binary logic based traditional designs, we use (incomplete) large parallel counters and large shift switch compressors, which are built based on shift switch logic, a logic with shift switches as logic elements performing modulo arithmetic operations on (non-binary) state signals. With the unique feature of shift switch logic our parallel multiplier schemes have shown superiority in speed and in area compactness. This is provided through the use of a stage-reduced partial product reduction network, the efficient signal interconnection and the simplified final carry lookahead adder. Compared to the well-known designs, our approach possesses higher regularity and simplicity on circuit structures, characterized by both the recursive shift switch networks which localize the major part of partial product reduction and the deliberated utilization of uneven arrival signals which minimize the delay of the multipliers.

A novel scheme for i gular parqllel-prefix adders

Abstract: A schematic of a new 64-bit adder is pre- sented in this paper. This adder uses the Manchester Carry Chain carry lookahead modules with spans of 4,3, and 2. Only the first level has intermediate outputs. Unlike carry-ripple adders at the output of the Spanning Tree Carry Lookahead Adder(SPT)(l,t) and the Recur- sive Carry-LookaheadCarry-Select Hybrid Adder (RCS)(3), the proposed Irregular Parallel-Prefix WP) adder provided parallel addition at the output thus signif- icantly reducing the number of transistors with a prom- ising compatible speed. This wifl cause a considerabIe improvement in cost-performance. Without a carry-skip circuit, this adder also works well with a carry-in of "1" based on Brent-Kung and Tyagi's lemmas (4$). Because the IPP adder is unidirectional, it is more appropriate for pipeline implementation. Preliminary simulation results by Mentor Graphics at static gate-level have indicated that IPP adders are faster than Tyagi's 16-bit, 32-bit and 64-bit Select-Prefix Adders(5). SPICE simulation at a transistor-level for a 16-bit IPP adder shows a speed of 1.756 ns. It reduces the transistor-count approximately by 21% compared to the RCS adder(3) and by 18% com- pared to the SPT adder( 1,2).

A dynamic four-bit carry lookahead adder circuit for complementary gallium arsenide (CGaAs) fabrication processes

Abstract: The design and implementation of three, 4-bit carry lookahead adders using Complementary Gallium Arsenide (CGaAs) HIGFETs is presented, including static, pipelined static and dynamic versions. The designs are compared for speed, power consumption and layout area. The dynamic implementation operates at the highest speed (1.2 GHz) and consumes the best power (0.01 /spl mu/W/MHz/gate).