Showing papers on "Carry-lookahead adder published in 1998"

A simplified architecture for module (2/sup n/+1) multiplication

Abstract: The module (2/sup n/+1) multiplication is widely used in the computation of convolutions and in RNS arithmetic and, thus, it is important to reduce the calculation delay. This paper presents a concept of a module (2/sup n/+1) carry save adder (MCSA) and uses two MCSAs to perform the residue reduction. We also apply Booth's algorithm to the module (2/sup n/+1) multiplication scheme in order to reduce the number of partial products. With these techniques, the new architecture reduces the multiplier's calculation delay and is suitable for VLSI implementation for moderate and large n (n/spl ges/16).

Mechanical Verification of Adder Circuits using Rewrite RuleLaboratory

Abstract: A methodology for mechanically verifying generic adder circuits is proposed using the rewrite-rule based theorem prover {\it Rewrite\ Rule\ Laboratory} ({\it RRL}). Proofs of properties of adder circuit descriptions are done by rewriting and induction. Carry lookahead adder circuit is described using {\it powerlists}, a data structure introduced by Misra to support {\it divide-and-conquer} strategy used for designing data-parallel algorithms. This description uses an algorithm for {\it parallel\ prefix} computation on powerlists due to Adams. Reasoning about properties of this algorithm can be of independent interest since parallel prefix operator has been found useful in many data-parallel algorithms. The correctness of the carry-lookahead adder (i.e., the adder indeed implements addition on numbers) is established by showing its equivalence to a recursive description of the ripple-carry adder, which is shown to correctly implement addition on natural numbers. The ripple carry adde r circuit is described in two different but equivalent ways: using powerlists employing the divide-and-conquer strategy, as well as using linear lists employing the linear decomposition strategy. The description of the ripple carry adder using powerlists is useful for showing equivalence of its input-output behavior to that of carry lookahead adder, whereas the description using linear lists is useful for showing its correctness with respect to addition on natural numbers. Descriptions of adder circuits using powerlists are based on Adams‘ work who also gave a hand proof of their correctness using the powerlist algebra. The emphasis in this paper is to {\it generate\ proofs\ mechanically\ by\ a\ theorem\ prover} . {\em RRL} exploits the algebraic laws of the powerlist algebra as rewrite rules, and uses heuristics for mechanizing proofs by induction using the cover set method to generate such proofs. The regularity in hardware circuits gets refl ected in compact descriptions generated using the divide-and-conquer strategy as well as in mechanically generated proofs by induction. Mechanical proofs generated by {\em RRL} closely follow the well-crafted hand-proofs which is quite encouraging. A comparison with Adams‘ hand generated proof is also made. There is strong evidence that the proposed methodology for generating proofs should scale up for large circuits exhibiting regularity that can be described using divide-and-conquer strategy in terms of powerlists.

1-of-4 multiplier

Abstract: The described multiplier provides the signed or unsigned product of a multiplicand and multiplier represented in preferably 1-of-4 N-NARY signals by performing a preferably radix-four Booth recoding of the multiplier, producing partial products using a plurality of Booth multiplexers, summing the partial productsto produce two intermediate partial products using a six-level Wallace tree, and summing the two intermediate partial products using a carry lookahead adder. The Booth encoding is performed at the dit level using encoding circuitry implemented in N-NARY logic.

Design of low power differential logic using adiabatic switching technique

Abstract: This paper presents a new adiabatic circuit technique called adiabatic differential cascode voltage switch with complementary pass-transistor logic tree (ADCPL). Power reduction is achieved by recovering the energy in the recover phase of the supply clock. Energy dissipation comparison with other logic circuits is performed. Simulation shows that for a pipelined ADCPL carry lookahead adder, a power reduction of 50% to 70% can be achieved over static CMOS case within a practical operation frequency range.

Pipelined GaAs carry lookahead adder

Abstract: Based on the recently introduced GaAs pseudo-dynamic latched logic, the authors present a new type of carry lookahead adder (CLA) which combines the benefits of 0.6 /spl mu/m E/D MESFET technology with the above mentioned class of logic. Consideration is given to power dissipation, taking into account that for high levels of integration, techniques to reduce the power budget are essential. As a result. The design of a four bit pipelined GaAs CLA operating at 800 MHz and exhibiting less than 1.8 mW of power dissipation is presented.

Efficient VLSI implementation of statistical carry lookahead adder

Abstract: A new efficient VLSI implementation of a statistical carry lookahead adder is presented. The new circuit does not require precharged input signals, and it can be used in practical asynchronous system design and in mixed logic design without any auxiliary circuitry. The circuit is realised in domino logic, and DCVSL gates are used for the critical path.

Current sensing differential logic (CSDL) for low-power and high-speed systems

Abstract: A new low-power high-speed glitch-free logic concept, Current Sensing Differential Logic (CSDL), is presented. This concept is developed for complex integrated systems of prime importance where the reliability in operation and design flexibility. These performance improvements of power and speed are enabled by restricting the internal voltage swings in the logic evaluation tree. Using the CSDL logic, a 64-bit carry lookahead adder is designed in a 0.6 /spl mu/m CMOS technology. The results of the post-layout simulation show that it achieves 2.9 ns delay with the power consumption of 21 mW at 50 MHz with clock buffer.