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Showing papers on "Carry-lookahead adder published in 1999"


Journal ArticleDOI
TL;DR: An energy-efficient carry-lookahead adder using reversible energy recovery logic (RERL), which is a new dual-rail reversible adiabatic logic, and an eight-phase, clocked power generator that requires an off-chip inductor is described.
Abstract: In this paper, we describe an energy-efficient carry-lookahead adder using reversible energy recovery logic (RERL), which is a new dual-rail reversible adiabatic logic. We also describe an eight-phase, clocked power generator that requires an off-chip inductor. For the energy-efficient design of reversible logic, we explain how to control the overhead of reversibility with a self-energy-recovery circuit. A test chip was implemented with a 0.8 /spl mu/m CMOS technology, which included two 16-bit carry-lookahead adders to allow fair comparison: an RERL one and a static CMOS one. Experimental results showed that the RERL adder had substantial advantages in energy consumption over the static CMOS one at low operating frequencies. We also confirmed that we could minimize the energy consumption in the RERL circuit by reducing the operating frequency until adiabatic and leakage losses were equal.

71 citations


Proceedings ArticleDOI
08 Jun 1999
TL;DR: The design of a highly re-configurable adder, which has been optimized for speed and area, is presented, which is the hybrid of binary carry lookahead adder of Brent, and carry select adder.
Abstract: This paper presents the design of a highly re-configurable adder, which has been optimized for speed and area. Since pass transistor based multiplexer is the fastest element in standard CMOS logic, we designed the adder using only multiplexers and 2-input inverted logic gates. This adder is the hybrid of binary carry lookahead adder of Brent, and carry select adder. By using the hybrid approach, the area and wiring of the adder is reduced by 1/2, keeping the adder delay proportional to O(log n). The critical path of the 68-bit partitioned adder consists of 7 two-to-one multiplexers and 1 XOR gate. The adder can be partitioned to support a variety of data formats, it can add two 64-bit-operands, four 32-bit operands, eight 16-bit operands, or sixteen and bit operands. The adder can be used for multi-media applications, and is well suited for VLIW processors. The adder is described in Verilog, and synthesized using Synopsys tool. The critical path delay of the 64-bit adder is 0.9 ns at typical conditions in standard cell 0.25 um technology.

26 citations


Journal ArticleDOI
TL;DR: This paper implements binary adders with threshold logic using a new methodology that introduces two innovations: the use of the input and output carries of each bit for obtaining all the sum bits and a modification of the classic carry lookahead adder technique that allows us to obtain the expressions of the generation and propagation carries in a more appropriate way for threshold logic.
Abstract: The central topic of this paper is the implementation of binary adders with threshold logic using a new methodology that introduces two innovations: the use of the input and output carries of each bit for obtaining all the sum bits and a modification of the classic carry lookahead adder technique that allows us to obtain the expressions of the generation and propagation carries in a more appropriate way for threshold logic In this way, it has been possible to systematize the process of design of a binary adder with threshold logic relating all its important parameters: number of bits of the operands, depth, size, maximum fan-in, and maximum weight The results obtained are an improvement on those published to date and are summarized as follows: Depth 2 adder: s=2n, w/sub max/=2/sup n/, f/sub max/=2n+1 Depth 3 adder: s=4n-2[n/[/spl radic/n]], w/sub max/=2[n/[/spl radic/n]], f/sub max/=2[n/[/spl radic/n]]+1 Depth d adder (asymptotic behavior): s=O(n), w/sub max/=O(2/sup d-1/spl radic/n/), f/sub max/=O(/sup d-1/spl radic/n/) If the weights are bounded by w/sub max/:n/sub max/=O(log/sup d-1/ w/sub max/), d/sub min/=O(log n/log(log w/sub max/))

20 citations


Journal ArticleDOI
TL;DR: This CSDL eliminates the timing constraints between the enable signal and input signals, which cause difficulties in design with conventional differential logic families, by employing a simple clocking scheme.
Abstract: In this paper, we present a highly reliable and flexible CMOS differential logic called current sensing differential logic (CSDL). This CSDL eliminates the timing constraints between the enable signal and input signals, which cause difficulties in design with conventional differential logic families, by employing a simple clocking scheme. The power-delay product of CSDL is also reduced by using a swing suppression technique. To verify the reliability and the applicability of the proposed CSDL in large very large-scale-integration systems, a 64-bit carry-lookahead adder has been fabricated in a 0.6 /spl mu/m CMOS technology. Experimental results show that the critical path delay is 3.5 ns with a power consumption of 27 mW at 50 MHz.

15 citations


Patent
30 Jul 1999
TL;DR: In this paper, a fully pipelined parallel multiplier with a fast clock cycle is presented, which consists of three units: a bit-product matrix unit, a reduction unit, and an addition unit.
Abstract: A fully pipelined parallel multiplier with a fast clock cycle. The pipelined parallel multiplier contains three units: a bit-product matrix unit, a reduction unit, and an addition unit. The bit-product matrix is configured to receive two binary numbers, a multiplier and a multiplicand. A bit-product matrix is formed based on these two numbers. The bit-product matrix unit forms a first pipeline stage. The bit-product matrix is latched to the reduction unit using d-type latch circuits. The reduction unit includes a plurality of reduction stages, with each reduction stage acting as a pipeline stage. The reduction unit reduces the matrix down to a two-row matrix. Intermediate results are latched from one stage to the next using d-type latch circuits. The reduction unit also contains a plurality of half-adder and full-adder circuits. The final two-row matrix formed by the reduction unit is then latched to an addition unit. The addition unit includes one or more stages of addition, with each stage also acting as a pipeline stage. Carry lookahead adder (CLA) circuits are cascaded to perform the addition, with one CLA per addition stage. Results from each addition stage are latched to the next stage using d-type latch circuits. The output from the final stage is the final product of the multiplication.

6 citations


Proceedings ArticleDOI
26 Oct 1999
TL;DR: It is shown that an efficient implementation of a self-timed statistical carry lookahead adder can be built from a Manchester carry chain by exploiting multiple-output DCVSL and reduces the number of transistors.
Abstract: We show that an efficient implementation of a self-timed statistical carry lookahead adder can be built from a Manchester carry chain. By exploiting multiple-output DCVSL, the presented implementation not only relieves the delay matching problem of previous design in completion detection but also reduces the number of transistors. The worst case delay is comparable to the previous design, and 25.8% of average power consumption is reduced.

5 citations


Patent
03 May 1999
TL;DR: The carry lookahead adder (100) as mentioned in this paper is characterized by a modified binary tree structure having carry generate/propagate signal operators (21, 31, 35, 41, 44, 48, 51, 23, 25, 33, 37, 42, 46, 75, 76, 77, 78, 79, 80, 81, 82, 51-54, 83-86, 55, 57, 59, 63, 56, 58, 61, 64) located in such a manner that the maximum internal block fanout is equal to (adder width)/8 for
Abstract: A carry lookahead adder (100) having a reduced internal block fanout which is achieved efficiently in terms of the silicon area needed to implement the carry lookahead adder (100). The carry lookahead adder (100) of the present invention is characterized by a modified binary tree structure having carry generate/propagate signal operators (21, 31, 35, 41, 44, 48, 51, 23, 25, 33, 37, 42, 46, 75, 76, 77, 78, 79, 80, 81, 82, 51-54, 83-86, 55, 57, 59, 63, 56, 58, 61, 64) located in such a manner that the maximum internal block fanout is equal to (adder width)/8 for adders having a width of at least 16 bits. For adders having a width of less than 16 bits, the internal block fanout is 2. The routing complexity is increased in order to implement redundant overlapping carry generate/propagate operations which, in turn, decreases the internal block fanout of the adder. However, increases in routing complexity can be accomplished within the minimum X-by-Y area of each stage of the adder. Therefore, the overall performance of the carry lookahead adder (100) of the present invention can be optimized while meeting minimum area requirements.

1 citations