Showing papers on "Carry-lookahead adder published in 2003"

A shared-well dual-supply-voltage 64-bit ALU

Abstract: A shared n-well layout technique is developed for the design of dual-supply-voltage logic blocks. It is demonstrated on a design of a 64-bit arithmetic logic unit (ALU) module in domino logic. The second supply voltage is used to lower the power of noncritical paths in the sparse, radix-4 64-bit carry-lookahead adder and in the loopback bus. A 3 mm/sup 2/ test chip in 0.18-/spl mu/m 1.8-V five-metal with local interconnect CMOS technology that contains six ALUs and test circuitry operates at 1.16 GHz at the nominal supply. For target delay increase of 2.8% energy savings are 25.3% using dual supplies, while for 8.3% increase in delay, 33.3% can be saved.

A 1.25 GHz 32-bit tree-structured carry lookahead adder using modified ANT logic

Abstract: In this work, a 32-bit tree-structured carry lookahead adder (CLA) is proposed by using the modified all-N-transistor (ANT) design. The 32-bit CLA not only possesses few transistor count, but also occupies a small area size. Moreover, the post-layout simulation results given by TimeMill show that the clock used in this 32-bit CLA can run up to 1.25 GHz at 3.3-V power supply. The output of the proposed CLA will be ready after 3.5 cycles. The proposed circuit is also easy to be expanded for long data additions. A physical chip is fabricated to verify the proposed circuit on silicon.

Structure and method for reducing mumber of carry lookahead adder stages in high-speed arithmetic units

Abstract: A carry-look-ahead adder for adding an addend and an augend and generating a final sum. The addend, augend, and final sum are binary numbers, each having a plurality of bits. Bits of the same order in the addend and the augend are organized into columns. The adder has at least one data reduction stage, each data reduction stage having at least one multi-column full adder. The data reduction stages use the columns of addend and augend bits to generate a reduced addend and a reduced augend, with the reduced augend having fewer bits than the augend. A generate/propagate calculation stage then uses the reduced addend and the reduced augend for calculating generate and propagate data, the generate/propagate calculation stage having been modified to account for the reduction of the addend and augend. A carry-generate stage then uses the generate and propagate data to generate at least one final carry. Finally, a final sum calculation stage uses the reduced addend, the reduced augend, and the final carries for calculating the final sum. The data reduction stages reduce the inputs to the generate/propagate calculation stage thereby reducing the number of inputs to the carry-generate circuit. With fewer inputs, the number of stages in the carry-generate circuit can be reduced, thus resulting in a faster implementation of the carry-look-ahead adder.

Adiabatic circuits: converter for static CMOS signals

Abstract: . Ultra low power applications can take great advantages from adiabatic circuitry. In this technique a multiphase system is used which consists ideally of trapezoidal voltage signals. The input signals to be processed will often come from a function block realized in static CMOS. The static rectangular signals must be converted for the oscillating multiphase system of the adiabatic circuitry. This work shows how to convert the input signals to the proposed pulse form which is synchronized to the appropriate supply voltage. By means of adder structures designed for a 0.13µm technology in a 4-phase system there will be demonstrated, which additional circuits are necessary for the conversion. It must be taken into account whether the data arrive in parallel or serial form. Parallel data are all in one phase and therefore it is advantageous to use an adder structure with a proper input stage, e.g. a Carry Lookahead Adder (CLA). With a serial input stage it is possible to read and to process four signals during one cycle due to the adiabatic 4-phase system. Therefore input signals with a frequency four times higher than the adiabatic clock frequency can be used. This reduces the disadvantage of the slow clock period typical for adiabatic circuits. By means of an 8 bit Ripple Carry Adder (8 bit RCA) the serial reading will be introduced. If the word width is larger than 4 bits the word can be divided in 4 bit words which are processed in parallel. This is the most efficient way to minimize the number of input lines and pads. At the same time a high throughput is achieved.

A pipelined clock-delayed domino carry-lookahead adder

Abstract: Clock-delayed (CD) domino is a dynamic logic family developed to provide both inverting and non-inverting logic on single-rail gates. It is self-timed and can be easily pipelined for superior speed performance which makes it an attractive option in high-speed logic implementation. This paper presents the design of two different high-speed pipeline configurations of a 32-bit carry look-ahead adder using CD domino gates utilizing efficient clocking methodology to reduce the overall critical path delay.

Faster shift value calculation using modified carry-lookahead adder

Abstract: Circuitry for reducing propagation delays in calculation of a value for use in a floating point multiply-accumulate operation. In the circuitry, a carry-save adder receives values of three input operands from three latches. A carry-lookahead adder receives the outputs from the carry-save adder and implements an XOR operation on a most-significant bit along with its own logic operation to produce a value for the floating point multiply-accumulate operation. Modification of the carry-lookahead adder to perform the XOR operation results in elimination of an entire stage of logic.

Algorithm and Structure Design of Logarithmic Skip Adder

Abstract: LSA (Logarithmic Skip Adder) Algorithm is introduced in this paper.LSA is a hybrid structure of carry skip adder and ELM carry lookahead adder,which replaces serial carry chain with binary tree structure.In structure design,a carry incorporated structure to include the primary carry input in carry chain is found to reduce logic depth.With its regular structure,32 bit LSA has a logic depth of 8 and a fanout no more than 5.Circuit simulating results in 0 25um CMOS process show a critical path delay of 760ps.