Showing papers on "Carry-lookahead adder published in 2005"

A 32-bit carry lookahead adder using dual-path all-N logic

Abstract: We have developed dual path all-N logic (DPANL) and applied it to 32-bit adder design for higher performance. The speed is significantly enhanced due to reduced capacitance at each evaluation node of dynamic circuits. The power saving is achieved due to reduced adder cell size and minimal race problem. Post-layout simulation results show that this adder can operate at frequencies up to 1.85 GHz for 0.35-/spl mu/m 1P4M CMOS technology and is 32.4% faster than the adder using all-N transistor (ANT). It also consumes 29.2% less power than the ANT adder. A 0.35-/spl mu/m CMOS chip has been fabricated and tested to verify the functionality and performance of the DPANL adder on silicon.

Pipelined Carry Lookahead Adder Design in Quantum-dot Cellular Automata

Abstract: Quantum-dot cellular automata (QCA) is a novel nanotechnology for electronic circuits. The QCA cell is a funda- mental building block. QCA circuits are different from transistor circuits mainly because the basic computational gate is a majority gate and interconnections consume time and area. It's easy to design a pipelined circuit and coplanar wire crossings for a two dimensional structure, but complex designs consume more time due to the wire. The estimation of timing is difficult until the layout is finished. This paper proposes a pipelined carry lookahead adder design in QCA. Using the QCADesigner, 4, 16, and 64 bit carry lookahead adders are designed and simulated. Those designs are compared with ripple carry adders according to the complexity, area, and timing. The final layouts show modular designs and small delays for the carry lookahead adder.

Energy efficient surfing [latchless pipelining technique]

Abstract: Surfing is a latchless pipelining technique where the propagation delays of gates and other logic functions are modulated to produce event attractors. We describe a test chip that demonstrates a surfing pipeline ring and then introduce new circuits that dramatically reduce the energy overhead for surfing. Our test chip implements a twelve-stage, surfing ring that supports two independent waves of computation without latches or other storage elements. We have operated the chip for over 48 hours and more than 2.6/spl times/10/sup 15/ surfing events without an error. However, the energy consumption of the ring is unacceptable for scaling to larger applications. Thus, we introduce a new family of surfing circuits that use less energy than their domino counterparts and provide a factor of up to 1.75 improvement by the Et/sup 2/ metric. We demonstrate this new family with the design of a carry lookahead adder.

The design of an asynchronous carry-lookahead adder based on data characteristics

Abstract: Addition is the most important operation in data processing and its speed has a significant impact on the overall performance of digital circuits. Therefore, many techniques have been proposed for fast adder design. An asynchronous ripple-carry adder is claimed to use a simple circuit implementation to gain a fast average performance as long as the worst cases input patterns rarely happen. However, based on the input vectors from a number of benchmarks, we observe that the worst cases are not exceptional but commonly exist. A simple carry-lookahead scheme is proposed in the paper to speed up the worst-case delay of a ripple-carry adder. The experiment result shows the proposed adder is about 25% faster than an asynchronous ripple-carry adder with only small area and power overheads.