Showing papers on "Carry-lookahead adder published in 2007"

Adder Designs and Analyses for Quantum-Dot Cellular Automata

Abstract: Quantum-dot cellular automata (QCA) is an emerging nanotechnology for electronic circuits. Its advantages such as faster speed, smaller size, and lower power consumption are very attractive. The fundamental device, a quantum-dot cell, can be used to make gates, wires, and memories. As such it is the basic building block of nanotechnology circuits. While the physical nature of the nanoscale materials is complicated, the circuit designer can concentrate on the logical and structural design, so the design effort is reduced. Because of its novelty, the current literature shows only simple circuit structures. So this paper broadens the QCA circuit designs with larger circuits and shows analyses based on those designs. This paper proposes three kinds of adder designs in QCA. Ripple carry adders, carry lookahead adders, and conditional sum adders are designed and simulated with several different operand sizes. The designs are compared according to complexity, area, and delay

A 0.13μm hardware-efficient probabilistic-based noise-tolerant circuit design and implementation with 24.5dB noise-immunity improvement

Abstract: As the size of CMOS devices is scaled down to the nanoscale level, noise interferences start to significantly affect the VLSI circuit performance Because the noise is random and dynamic in nature, a probabilistic-based approach is more suitable to handle signal errors than the conventional deterministic circuit designs However, probabilistic-based designs cost larger hardware area In this paper, we design and implement a hardware-efficient probabilistic-based noise-tolerant circuit, an 8-bit Markov random field carry lookahead adder (MRF_CLA), in 013 mum CMOS process technology The measurement results show that the proposed MRF_CLA can provide 245 dB of noise-immunity enhancement as compared with its conventional CMOS design Moreover, the transistor count can be saved 42% as compared to the state-of-art MRF design [1]

Verilog HDL: Digital Design and Modeling

Abstract: PREFACE INTRODUCTION History of HDL Verilog HDL IEEE Standard Features Assertion Levels OVERVIEW Design Methodologies Modulo-16 Synchronous Counter Four-Bit Ripple Adder Modules and Ports Designing a Test Bench for Simulation Construct Definitions Introduction to Dataflow Modeling Two-Input Exclusive-OR Gate Four 2-Input AND Gates With Delay Introduction to Behavioral Modeling Three-Input OR Gate Four-Bit Adder Modulo-16 Synchronous Counter Introduction to Structural Modeling Sum-of-Products Implementation Full Adder Four-Bit Ripple Adder Introduction to Mixed-Design Modeling Full Adder Problems LANGUAGE ELEMENTS Comments Identifiers Keywords Bidirectional Gates Charge Storage Strengths CMOS Gates Combinational Logic Gates Continuous Assignment Data Types Module Declaration MOS Switches Multiple-Way Branching Named Event Parameters Port Declaration Procedural Constructs Procedural Continuous Assignment Procedural Flow Control Pull Gates Signal Strengths Specify Block Tasks and Functions Three-State Gates Timing Control User-Defined Primitives Value Set Data Types Net Data Types Register Data Types Compiler Directives Problems EXPRESSIONS Operands Constant Parameter Net Register Bit-Select Part-Select Memory Element Operators Arithmetic Logical Relational Equality Bitwise Reduction Shift Conditional Concatenation Replication Problems GATE-LEVEL MODELING Multiple-Input Gates Gate Delays Inertial Delay Transport Delay Module Path Delay Additional Design Examples Iterative Networks Priority Encoder Problems USER-DEFINED PRIMITIVES Defining a User-Defined Primitive Combinational User-Defined Primitives Map-Entered Variables Sequential User-Defined Primitives Level-Sensitive User-Defined Primitives Edge-Sensitive User-Defined Primitives Problems DATAFLOW MODELING Continuous Assignment Three-Input AND Gate Sum Of Products Reduction Operators Octal-To-Binary Encoder Four-To-One Multiplexer Four-To-One Multiplexer Using The Conditional Operator Four-Bit Adder Carry Lookahead Adder Asynchronous Sequential Machine Pulse-Mode Asynchronous Sequential Machine Implicit Continuous Assignment Delays Problems BEHAVIORAL MODELING Procedural Constructs Initial Statement Always Statement Procedural Assignments Intrastatement Delay Interstatement Delay Blocking Assignments Nonblocking Assignments Conditional Statement Case Statement Loop Statements For Loop While Loop Repeat Loop Forever Loop Block Statements Sequential Blocks Parallel Blocks Procedural Continuous Assignment Assign ... Deassign Force ... Release Problems STRUCTURAL MODELING Module Instantiation Ports Unconnected Ports Port Connection Rules Design Examples Gray-To-Binary Code Converter BCD-To-Decimal Decoder Modulo-10 Counter Adder/Subtractor Four-Function ALU Adder and High-Speed Shifter Array Multiplier Moore-Mealy Synchronous Sequential Machine Moore Synchronous Sequential Machine Moore Asynchronous Sequential Machine Moore Pulse-Mode Asynchronous Sequential Machine Problems TASKS AND FUNCTIONS Tasks Task Declaration Task Invocation Functions Function Declaration Function Invocation Problems ADDITIONAL DESIGN EXAMPLES Johnson Counter Counter-Shifter Universal Shift Register Hamming Code Error Detection and Correction Booth Algorithm Moore Synchronous Sequential Machine Mealy Pulse-Mode Asynchronous Sequential Machine Mealy One-Hot Machine BCD Adder/Subtractor BCD Addition BCD Subtraction Pipelined RISC Processor Instruction Cache Instruction Unit Decode Unit Execution Unit Register File Data Cache RISC CPU Top System Top Problems APPENDIX A Event Queue Event Handling for Dataflow Constructs Event Handling for Blocking Assignments Event Handling for Nonblocking Assignments Event Handline for Mixed Blocking and Nonblocking Assignments APPENDIX B Verilog Project Procedure APPENDIX C Answers to Selected Problems Overview Language Elements Expressions Gate Level Modeling User-Defined Primitives Dataflow Modeling Behavioral Modeling Structural Modeling Tasks and Functions Additional Design Examples INDEX

Post-layout comparison of high performance 64b static adders in energy-delay space

Abstract: Our objective was to determine the most energy efficient 64 b static CMOS adder architecture, for a range of high-performance delay targets. We examine extensively carry-lookahead (CLA) and carry-select adders with a wide range of tradeoffs in logic levels, fanouts and wiring complexity. We propose sparse CLA adder architectures based on buffering techniques to reduce logic redundancy and improve energy efficiency. All the designs were implemented using an energy-delay layout optimization flow with full RC extraction. Our new 64 b adder designs have a relative delay as low as 9.9 F04 (fanout-offour inverter) delays and promise better scaling for smaller technology nodes. They yield the best energy efficiency for a wide range of delay targets and are 30%, 15% and 7% more energy efficient than full Kogge-Stone, sparse-2 Kogge-Stone and Han-Carlson, respectively, at the fastest points. They consume only about 1/3 the energy of dynamic adders.

15GHz low-voltage-swing carry-lookahead adder

Abstract: We describe a high speed adder that employs a carry-lookahead structure and uses low-voltage-swing pass-transistor-based Manchester carry chain. This structure is implemented in 65nm technology and accommodates 15GHz clock frequency at the slowest corner which is 20% higher than the highest speed in the previously studied high-speed structures.

Low-power eight-bit SCSDL CLA with a novel split-level charge-sharing differential logic (SCSDL)

Abstract: A novel logic family, called Split-Level Charge-Sharing Differential Logic (SCSDL), is proposed in this letter. The SCSDL uses the charge recycling technique to reduce power dissipation of differen...

IF-THEN Adder Application in Online DALUT Implementation

Abstract: This paper presents the application of a proposed if-then rule based adder in implementing distributed arithmetic online lookup table (DALUT). The online DALUT development and implementation is a continuation of our previous work where we proposed this idea and use it in designing finite impulse (FIR) filter. In our LUT architecture we have been able to overcome the major disadvantage of the basic DA architecture reported as the exponential growth of the LUT size with the number of input variables. The if-then adder was proposed in another work where it shows an efficient performance when compared with the well known ripple carry adder (RCA) and the carry lookahead adder (CLA). The online DALUT with the if-then adder was applied in designing 70-tap finite impulse response pulse shaping filter and some other different order FIR filters. The design was coded with Verilog hardware description language (verilog HDL) and synthesized using the Xilinx technology after being simulated with ModelSim 7.5g. The synthesis report shows that the design preference when using the if-then adder more efficient than in the case of the RCA and CLA adder. The maximum frequency reached with the design using the if-then adder was 85.095MHz, whereas, when using CLA and RCA adders it 77.936MHz and 77.042MHz respectively. Finally the design has been successfully downloaded to Virtex-II FPGA fg456 and tested with the TLA5201 logic analyzer.