Showing papers on "Carry-lookahead adder published in 2009"

Performance Analysis of Fast Adders Using VHDL

Abstract: This paper presents performance analysis of different Fast Adders. The comparison is done on the basis of three performance parameters i.e. Area, Speed and Power consumption. Further, we present a design methodology of hybrid carry lookahead/carry skip adders (CLSKAs). This modified carry skip adder is modeled by using both fix and variable block size. In conventional carry skip adder, each block consists of ripple carry adder and skip logic is used after each block to generate carry for next block. The speed of operation depends on carry propagation from previous block to next block. In CLSKAs, we use carry lookahead logic in each block to generate carry for next block. The modified carry skip adders presented in this paper provides better speed and power consumption as compare to conventional carry skip adder and other adders like ripple carry adder, carry lookahead adder, Ling adder, carry select adder. The modified carry skip adders with fix block require few more CLB’s because of Carry lookahead logic, whereas with variable block scheme, area optimization is achieved.

Design and Implementation of Cost-Effective Probabilistic-Based Noise-Tolerant VLSI Circuits

Abstract: As the size of CMOS devices is scaled down to nanometers, noise can significantly affect circuit performance. Because noise is random and dynamic in nature, a probabilistic-based approach is better suited to handle these types of errors compared with conventional CMOS designs. In this paper, we propose a cost-effective probabilistic-based noise-tolerant circuit-design methodology. Our cost-effective method is based on master-and-slave Markov random field (MRF) mapping and master-and-slave MRF logic-gate construction. The resulting probabilistic-based MRF circuit trades hardware cost for circuit reliability. To demonstrate a noise-tolerant performance, an 8-bit MRF carry-lookahead adder (MRF_CLA) was implemented using the 0.13-mum CMOS process technology. The chip measurement results show that the proposed master-and-slave MRF_CLA can provide a 7.00 times 10-5 bit-error rate (BER) under 10.6-dB signal-to-noise ratio, while the conventional CMOS_CLA can only provide 8.84 times 10-3 BER. Because of high noise immunity, the master-and-slave MRF_CLA can operate under 0.25 V to tolerate noise interference with only 1.9 muW/MHz of energy consumption. Moreover, the transistor count can be reduced by 42% as compared with the direct-mapping MRF_CLA design .

A fast low-power modulo 2 n +1 multiplier design

Abstract: Modulo 2n + 1 multipliers are the primitive computational logic components widely used in residue arithmetic, digital signal processing and cryptography. In this work, a fast low-power hardware implementation of modulo 2n + 1 multiplier is proposed and validated. The proposed hardware architecture is based on the efficient compressors and modulo carry look-ahead adders as the basic building blocks. The modulo carry lookahead adder uses the sparse-tree adder technique to achieve better speed. The resulting implementations are compared both qualitatively and quantitatively, in standard CMOS cell technology, with the existing implementations. The results show that the proposed implementation is considerably faster and consume significantly less power than similar hardware implementations making them a viable option for efficient designs.

Circuit Design for A Measurement-Based Quantum Carry-Lookahead Adder

Abstract: We present the design and evaluation of a quantum carry-lookahead adder (QCLA) using measurement-based quantum computation (MBQC), called MBQCLA. QCLA was originally designed for an abstract, concurrent architecture supporting long-distance communication, but most realistic architectures heavily constrain communication distances. The quantum carry-lookahead adder is faster than a quantum ripple-carry adder; QCLA has logarithmic depth while ripple adders have linear depth. MBQCLA utilizes MBQC's ability to transfer quantum states in unit time to accelerate addition. MBQCLA breaks the latency limit of addition circuits in nearest neighbor-only architectures : compared to the $\Theta(n)$ limit on circuit depth for linear nearest-neighbor architectures, it can reach $\Theta(log n)$ depth. MBQCLA is an order of magnitude faster than a ripple-carry adder when adding registers longer than 100 qubits, but requires a cluster state that is an order of magnitude larger. The cluster state resources can be classified as computation and communication; for the unoptimized form, $\approx$ 88 % of the resources are used for communication. Hand optimization of horizontal communication costs results in a $\approx$ 12% reduction in spatial resources for the in-place MBQCLA circuit. For comparison, a graph state quantum carry-lookahead adder (GSQCLA) uses only $\approx$ 9 % of the spatial resources of the MBQCLA.

An improved 32-bit carry-lookahead adder with Conditional Carry-Selection

Abstract: An improved 32-bit carry-lookahead adder (CLA) with Conditional Carry-Selection (CSS) is proposed in this paper. The new adder is compared with Serial Adder and pure Carry-Lookahead Adder. The three adders is simulated in FPGA circuits, the results show that the propagation time of the carry of the new 32-bit adder is reduced 26% compared with Serial Adder and 3.17% with pure Carry-Lookahead Adder.

Resources for Measurement-Based Quantum Carry-Lookahead Adder

Abstract: We present the design of a quantum carry-lookahead adder using measurement-based quantum computation. QCLA utilizes MBQC`s ability to transfer quantum states in unit time to accelerate addition. The quantum carry-lookahead adder (QCLA) is faster than a quantum ripple-carry adder; QCLA has logarithmic depth while ripple adders have linear depth. QCLA is an order of magnitude faster than a ripple-carry adder when adding registers longer than 100 qubits but requires a cluster state that is an order of magnitude larger. Hand optimization results in a $\approx$ 26% reduction in spatial resources for the circuit.

A Measurement-Based Form of the Out-of-Place Quantum Carry-Lookahead Adder

Abstract: We present the design of a quantum carry-lookahead adder using measurement-based quantum computation. The quantum carry-lookahead adder (QCLA) is faster than a quantum ripple-carry adder; QCLA has logarithmic depth while ripple adders have linear depth. Our design is evaluated in terms of number of time steps and the total number of qubits used.