Showing papers on "Carry-lookahead adder published in 2010"

Circuit design for a measurement-based quantum carry-lookahead adder

Abstract: We present the design and evaluation of a quantum carry-lookahead adder (QCLA) using measurement-based quantum computation (MBQC), called MBQCLA. QCLA was originally designed for an abstract, concurrent architecture supporting long-distance communication, but most realistic architectures heavily constrain communication distances. The quantum carry-lookahead adder is faster than a quantum ripple-carry adder; QCLA has logarithmic depth while ripple adders have linear depth. MBQCLA utilizes MBQC's ability to transfer quantum states in unit time to accelerate addition. MBQCLA breaks the latency limit of addition circuits in nearest neighbor-only architectures: compared to the Θ(n) limit on circuit depth for linear nearest-neighbor architectures, it can reach Θ(log n) depth. MBQCLA is an order of magnitude faster than a ripple-carry adder when adding registers longer than 100 qubits, but requires a cluster state that is an order of magnitude larger. The cluster state resources can be classified as computation ...

Irreversible bit erasures in binary adders

Abstract: The ultra-high density integrated circuits based on nanodevices will suffer from heat dissipation due to irreversible information erasure, limiting the reachable operating frequencies This paper studies the amount of logical bits lost in standard binary adder structures, which are shown to be sub-optimal when compared with the theoretical limit The analysis covers the pipelined ripple carry adder, the carry lookahead adder, and the conditional sum adder proposed for quantum-dot cellular automata implementation The study focuses on majority logic circuits, available also in many other technologies

Analysis of results obtained with a new proposed low area low power high speed fixed point adder

Abstract: Integer addition is one of the most important operations in digital computers digital signal processing and. In fact the speed of adders affects the speed and performance of their processors. In digital signal processing, multiply and accumulate (MAC) unit plays an important role when designing digital filters. However, this role is doubled when multiplierless techniques such as distributed arithmetic (DA) are applied. In such techniques, the addition operation is the main scale when specifying some of the design parameters such as operation speed, design area, and the power consumed. This paper discusses the results obtained from the design analyzer for the proposed addition circuit together with the results obtained for the two most common adders i.e. the carry lookahead adder (CLA) and the ripple carry adder (RCA). The results obtained for the three different adders show that the proposed addition circuit has lowest area, lowest power consumption. On the other hand, the proposed adder has an operation speed higher than the RCA and a very close to the speed of the CLA. it is worth to mention here that the proposed design is based on the concept of applying a set of if-then rules. This set of rules calculates the out sum and carry in human-like way of processing.

Investigation of properties of 36-bit adders for creation of DSP blocks on FPGA

Abstract: In this paper 36-bit ripple-carry, carry-skip, carry-select and carry-lookahead adders intended for using in field programmable gate arrays are investigated. These schemes implemented in CMOS 0.18 µm technology are compared for their performance. The size of adders is estimated.

Arithmetic operators based on the binary stored-carry-or-borrow representation

Abstract: We introduce implementations of arithmetic operators based on the binary stored-carry-or-borrow (BSCB) representation Several BSCB arithmetic elements, including full-adder, ripple-carry adder, and carry-lookahead adder are presented, followed by detailed design of an array multiplier In the latter design, the conventional initial AND matrix is transformed and expressed with a redundant radix-2 representation Each line of the resulting matrix is processed by an accumulation operator with the BSCB representation Due to a specific property of the multiplication process, this operator is simpler than a standard full-adder cell in terms of gate count, while maintaining the same propagation latency The entire multiplier is implemented with only XOR and AND gates, thus improving its testability and reliability