Showing papers on "Carry-lookahead adder published in 2011"
TL;DR: An all-optical prefix tree adder with the help of a terahertz optical asymmetric demultiplexer (TOAD) using a set of optical switches is proposed and the theoretical model is presented and verified through numerical simulation.
Abstract: We propose and describe an all-optical prefix tree adder with the help of a terahertz optical asymmetric demultiplexer (TOAD) using a set of optical switches. The prefix tree adder is useful in compound adder implementation. It is preferred over the ripple carry adder and the carry lookahead adder. We also describe the principle and possibilities of the all-optical prefix tree adder. The theoretical model is presented and verified through numerical simulation. The new method promises higher processing speed and accuracy. The model can be extended for studying more complex all-optical circuits of enhanced functionality in which the prefix tree adder is the basic building block.
5 citations
01 Jan 2011
TL;DR: In this article, an all-optical prefix tree adder with the help of a terahertz optical asymmetric demultiplexer (TOAD) using a set of optical switches is proposed.
Abstract: We propose and describe an all-optical prefix tree adder with the help of a terahertz optical asymmetric demultiplexer (TOAD) using a set of optical switches. The prefix tree adder is useful in compound adder implementation. It is preferred over the ripple carry adder and the carry lookahead adder. We also describe the principle and possibilities of the all-optical prefix tree adder. The theoretical model is presented and verified through numerical simulation. The new method promises higher processing speed and accuracy. The model can be extended for studying more complex all-optical circuits of enhanced functionality in which the prefix tree adder is the basic building block.
4 citations
27 Jun 2011
TL;DR: The logic design of ALU, an important constituent part of CPU, is described, which reduces the size of project effectively, accordingly improves the performance of the ALU and effectively combines the design idea of two-bit-in-one-group and conditional sum.
Abstract: The logic design of ALU, an important constituent part of CPU, is described in this paper. The application of the reconfigurable technology restructures the 8-bit, 16-bit, 32-bit arithmetic and logic operation, performs the arithmetic and logic operation simultaneously, and supports SIMD instructions. This design reduces the size of project effectively, accordingly improves the performance of the ALU. The adder in this design effectively combines the design idea of two-bit-in-one-group and conditional sum, and takes the optimization measures of Manchester carry chain and carry lookahead adder, which makes the basic addition unit increased in speed, reduced in size, and meanwhile lowered in power consumption. The length of the critical path in this design is 13-level logic gates. A simulation of this design has been completed, using the standard SMIC 0.18 µm library, and the anticipative performance index has been achieved.