Showing papers on "Carry-lookahead adder published in 2013"

Implementation of a high speed multiplier using carry lookahead adders

Abstract: This paper examines a modification to the Wallace/Dadda Multiplier to use carry lookahead adders instead of full adders to implement the reduction of the bit product matrix into the two numbers that are summed to make the product. Four bit carry lookahead adders are used in the reduction in place of individual full adders. Each carry lookahead adder reduces up to 9 partial products (instead of 3 with a full adder) while taking the same amount of time. This leads to fewer reduction stages than a traditional Wallace/Dadda Multiplier. The results show that 1 fewer stage is required for 4 by 4, 8 by 8, and 16 by 16 bit multipliers and 2 stages are saved for larger multipliers.

Improved non-restoring division algorithm with dual path calculation

Abstract: This paper focuses on improving the performance of non-restoring division by reducing the delay. To improve its performance, two new approaches are proposed here. For the first proposed approach, a novel method to find a quotient bit for every iteration, which hides the total delay of the multiplexer with dual path calculation is presented. The second new method uses a modified Most Significant Carry (MSC) generator, which determines the sign of each remainder faster than a carry lookahead adder. This reduces the total delay.

A New network multiplier using modified high order encoder and optimized hybrid adder in CMOS technology

Abstract: In this paper, a new low power, high speed network multiplier is presented. For increasing performance of multiplier, a novel modified high-order encoder is proposed. Previous encoder s have complicated hardware and their ability to decrease number of input operands is low. Presented encoder uses high-order algorithm and therefore reduces number of partial products efficiently. A new hybrid adder is presented which uses ideas of carry lookahead adder and ripple carry adder to modify final adder architecture. Previous carry lookahead adders have large carry network and their ability to decrease noise margin is low. It uses a DCVS carry network, which provides high speed and less wiring problems in compare with previous algorithms. Proposed hybrid adder has major effect on multiplier efficiency. A new network array is presented which uses high performance modules. Using a new algorithm, this study reduces critical path of tree multiplier. A novel counter is implemented which uses less transistor count and less power consumption in compare with previous algorithms. This counter uses pass transistor technology. Transistor connections, in mentioned counter are implemented in a new efficient way. The new multiplier has better efficiency in different electronic and algorithmic parameters in compare with previous implementations.

Threshold logic type carry lookahead adder comprising SET/MOS (Single Electron Transistor/Metal Oxide Semiconductor) hybrid circuit

Abstract: The utility model relates to a threshold logic type carry lookahead adder comprising a SET/MOS (Single Electron Transistor/Metal Oxide Semiconductor) hybrid circuit, which comprises a carry lookahead logic module, a first additive operation module and a second additive operation module; by utilizing the Coulomb blockade oscillation effect and multi-grid input characteristic of a single electron transistor and MOS transistor structure, the threshold logic-based carry lookahead adder comes into being. Because of the powerful logic function of threshold logic, the circuit only consists of ten threshold logic gates, and only thirty elements are used by the entire circuit. Compared with a conventional pure CMOS (Complementary Metal Oxide Semiconductor) carry lookahead adder, the circuit structure of the threshold logic type carry lookahead adder is greatly simplified, the number of transistors is remarkably reduced, and thereby the power consumption of the circuit is further reduced. The threshold logic type carry lookahead adder is expected to be applied in the fields of microprocessors, digital signal processors and the like, and can be in favor of further reducing the power consumption of circuits, save the chip area and increase the integration degree of circuits.

Reduced Complexity Hybrid Ripple Carry Lookahead Adder

Abstract: In this paper we discuss Hybrid Ripple Carry Lookahead Adder (HRCLA), which is a hybrid between Carry Lookahead Adder (CLA) and ripple adder (RA). In HRCLA time is traded off for area and power. HRCLA has been designed by rippling the last carry bit of a 4-bit CLA. HRCLA extracts the traits of Carry Lookahead Adders (CLA) speed and ripple adders (RA), area. A four bit proposed HRCLA has been implemented in Cadence using 45nm technology; the implementation results showed 12.2 %Area, 4.6 % power improvement and 14.01 % critical path delay overhead over CLA.

A Novel Ripple/Carry Lookahead Hybrid Carry Select Adder Architecture

Abstract: In this paper, two general architectures of Carry Select Adder (CSA) have been introduced for high speed addition. These CSA architectures utilize the hybridized structure of Carry Lookahead Adder (CLA) and Ripple Carry Adder (RCA). In these architectures the critical path delay has been reduced by reducing the number of multiplexer stages. The proposed designs are compared with regular CSA based on RCA. The second architecture showed 11.3%, 3.9% improvement in delay and an overhead of 13% in area.

Comparative Analysis of CMOS Transmission Gate Based Adders

Abstract: The adder is the most commonly used arithmetic block of the Central Processing Unit (CPU) and Digital Signal Processing (DSP), therefore its performance and power optimization is of utmost importance. In realizing modern Very Large Scale Integration (VLSI) circuits, low-power and high-speed are the two predominant factors which need to be considered. There always exists a trade-off between the design parameters such as speed, power consumption, and area We designed three different types of 4-bit transmission gate based adders namely Ripple Carry Adder, Carry Select Adder and Carry Lookahead Adder We compared the different adders on basis of no. of transistors, the average power consumption and delay. The simulation results are taken for 180nm technology with the help of Tanner (T-spice) simulation tool.

Development of optimum addition algorithm using modified parallel hybrid signed digit (MPHSD) technique

Abstract: Signed digit (SD) number systems provide the possibility of constant-time addition, where interdigit carry propagation is eliminated. In this paper, two classes of parallel adder are surveyed with an asynchronous adder based on their delay, area and power characteristics. With the development of high speed processors, a tradeoff is always required between area and execution time to yield the most suitable implementation with low power consumption. In this paper, we proposed an optimum high speed fast adder algorithm by using signed and hybrid signed digit algorithms. This modified parallel hybrid signed digit (MPHSD) adder has high speed and less area as compare to conventional adders like ripple carry adder and carry lookahead adder. The MPHSD adder require few more configuration logic blocks (CLB's) because of redundant logic to optimize execution time with area and power. A relative merits and demerits is also evaluated by performing a detailed analysis in terms of its cost and performance.