Showing papers on "Carry-lookahead adder published in 2014"
06 Mar 2014
TL;DR: In Very Large Scale Integration (VLSI) designs, Parallel prefix adders (PPA) have the better delay performance and these adders' delay, power and area are investigated and compared finally.
Abstract: In Very Large Scale Integration (VLSI) designs, Parallel prefix adders (PPA) have the better delay performance This paper investigates four types of PPA's (Kogge Stone Adder (KSA), Spanning Tree Adder (STA), Brent Kung Adder (BKA) and Sparse Kogge Stone Adder (SKA)) Additionally Ripple Carry Adder (RCA), Carry Lookahead Adder (CLA) and Carry Skip Adder (CSA) are also investigated These adders are implemented in verilog Hardware Description Language (HDL) using Xilinx Integrated Software Environment (ISE) 132 Design Suite These designs are implemented in Xilinx Virtex 5 Field Programmable Gate Arrays (FPGA) and delays are measured using Agilent 1692A logic analyzer and all these adder's delay, power and area are investigated and compared finally
32 citations
01 Nov 2014
TL;DR: This paper has designed High Speed Carry Save Adder (CSA) using Carry Look ahead adder in the final stage instead of using conventional ripple carry adder so that speed increases by 27.5%.
Abstract: Addition is one of the essential operations in Digital Signal Processing (DSP) applications which includes Fast Fourier Transform (FFT), Digital filters, multipliers etc. With the advancements in technology, research is still going on to design a adder that performs addition in flash of time. One of such high speed adder is Carry Save Adder (CSA). In this paper we have designed High Speed Carry Save Adder (CSA) using Carry Look ahead adder in the final stage instead of using conventional ripple carry adder [1] so that speed increases by 27.5%.
26 citations
TL;DR: A novel carry lookahead adder design is presented with multiple error detection/correction capability and it is analytically shown that this architecture has more reliability than the others, and the hardware implementation reveals thatThis architecture incurs much lower hardware overheads relative to traditional architectures while it provides higher error detection andcorrection efficiency.
15 citations
09 Jul 2014
TL;DR: Experimental result shows that the optical cost and delay incurred in staircase structured reversible implementation of CLA are much less than those proposed in the recently reported works.
Abstract: In this work, we present an efficient reversible implementation of Carry-Lookahead Adder (CLA) in all-optical domain. Now-a-days, semiconductor optical amplifier (SOA)-based Mach -- Zehnder interferometer (MZI) plays a vital role in the field of ultra-fast all-optical signal processing. We have used all optical based Mach-Zehnder Interferometer (MZI) switches to design the CLA circuit implementing reversible functionality. Two approaches are proposed for designing the CLA circuit. First, we propose a hierarchical approach for implementation of 2n-bit reversible CLA. In the second approach, we remove the drawback of hierarchical CLA and improve the design by implementing non-modular staircase structure of n-bit reversible CLA. The design complexities of both the approaches are computed. Experimental result shows that the optical cost and delay incurred in staircase structured reversible implementation of CLA are much less than those proposed in the recently reported works.
14 citations
31 Dec 2014
TL;DR: The purpose of this work is to propose the design of an 8-bit ALU which supports 4-bit multiplication and the designs can be designed by using verilog or VHDL and can also be designed on Cadence Virtuoso platform.
Abstract: An arithmetic logic unit acts as the basic building blocks or cell of a central processing unit of a computer. And it is a digital circuit comprised of the basic electronics components, which is used to perform various function of arithmetic and logic and integral operations further the purpose of this work is to propose the design of an 8-bit ALU which supports 4-bit multiplication. Thus, the functionalities of the ALU in this study consist of following main functions like addition also subtraction, increment, decrement, AND, OR, NOT, XOR, NOR also two complement generation Multiplication. And the functions with the adder in the airthemetic logic unit are implemented using a Carry Look Ahead adder joined by a ripple carry approach. The design of the following multiplier is achieved using the Booths Algorithm therefore the proposed ALU can be designed by using verilog or VHDL and can also be designed on Cadence Virtuoso platform.
7 citations
24 Mar 2014
TL;DR: A variable threshold feedback equalizer circuit with combinational logic blocks is proposed to mitigate the timing errors, which can be leveraged to reduce the dominant leakage energy by scaling supply voltage or decreasing the propagation delay at the fixed supply voltage.
Abstract: Low energy has become one of the primary constraint in the design of digital VLSI circuits in recent years. Minimum-energy consumption can be achieved in digital circuits by operating in the sub-threshold regime. However, in this regime process variation can result in up to an order of magnitude variations in Ion/Ioff ratios leading to timing errors, which can have a detrimental impact on the functionality of the sub-threshold circuits. These timing errors become more frequent in scaled technology nodes where process variations are highly prevalent. Therefore, mechanisms to mitigate these timing errors while minimizing the energy consumption in sub-threshold circuits are required. In this paper, we propose the use of a variable threshold feedback equalizer circuit with combinational logic blocks to mitigate the timing errors, which can then be leveraged to reduce the dominant leakage energy by scaling supply voltage or decreasing the propagation delay. At the fixed supply voltage, we can decrease the propagation delay of the critical path using equalizer circuits and, correspondingly decrease the leakage energy consumption. For a 8-bit carry lookahead adder designed in UMC 130 nm process, the operating frequency can be increased by 22.87% (on average), while reducing the leakage energy by 22.6% in the sub-threshold regime. Overall the feedback equalization technique provides up to 35.4% lower energy-delay product compared to the conventional non-equalized logic. Alternately, for a 8-bit carry lookahead adder, the proposed technique enables us to reduce the critical voltage (beyond which timing errors occur) from 300 mV (nominal design) to 270 mV (design with feedback circuit), and provides a 16.72% decrease in energy per operation while maintaining performance.
6 citations
TL;DR: A proposed carry- lookahead adder (PCLA) is designed using a new method that uses NAND gate for modification which helps in reducing the power- delay product (PDP) for high performance applications.
Abstract: This paper presents a comparative research of low-power and high-speed 4-bit full adder circuits. The represen- tative adders used are a ripple carry adder (RCA) and a carry-lookahead adder (CLA). We also design a proposed carry- lookahead adder (PCLA) using a new method that uses NAND gate for modification which helps in reducing the power- delay product (PDP) for high performance applications. To yield more realistic rise and fall times in the simulations, lay- outs have been made in a 0.13 � m process for the RCA circuit, CLA circuit and PCLA circuit. The layouts designed were simulated by HSPICE based on 130 nm CMOS technology at 1.2 V supply voltages. Four sets of frequencies were oper- ated: 10 MHz, 50 MHz, 100 MHz and 500 MHz with 50% duty cycle in different technology corner models. A compre- hensive comparison and analysis were also carried out to test the performance of the adders. The three adders also yield different performances in terms of power consumption, PDP, and area. The simulation results of this research are ex- pected to help designers to select the appropriate 4-bit adder cell that meets their specific applications.
3 citations
TL;DR: Two basic cells UCA and UCS for 3N and N/3 operations are introduced and their speed performances are estimated based on the delay data of standard cell library in TSMC 0.18µm CMOS process, showing that the 16-bit UCA-based RCA is about 3 times faster than the conventional FA- based RCA and even 25% faster thanThe FA-based CLA.
Abstract: SUMMARY This study presents efficient algorithms for performing multiply-by-3 (3N) and divide-by-3 (N/3) operations with the additions and subtractions, respectively. No multiplications and divisions are needed. Full adder (FA) and full subtractor (FS) can be implemented to realize the N3 and N/3 operations, respectively. For fast hardware implementation, this paper introduces two basic cells UCA and UCS for 3N and N/3 operations, respectively. For 3N operation, the UCA-based ripple carry adder (RCA) and carry lookahead adder (CLA) designs are proposed and their speed performances are estimated based on the delay data of standard cell library in TSMC 0.18µm CMOS process. Results show that the 16-bit UCA-based RCA is about 3 times faster than the conventional FA-based RCA and even 25% faster than the FA-based CLA. The proposed 16-bit and 64-bit UCA-based CLAs are 62% and 36% faster than the conventional FA-based CLAs, respectively. For N/3 operations, ripple borrow subtractor (RBS) is also presented. The 16-bit UCS-based RBS is about 15.5% faster than the 16-bit FS-based RBS.
3 citations
01 Jan 2014
TL;DR: This paper deals with the design & analysis of Carry Select Adder (CSLA) & Carry lookahead adder (CLA) & the simulated results on the basis area are compared.
Abstract: This paper deals with the design & analysis of Carry Select Adder (CSLA) & Carry lookahead adder (CLA). Adders are designed using 0.18µm CMOS process technology & simulated with Modelsim6.3f. The adder designs, Regular CSLA, modified CSLA using BEC, modified CSLA without using multiplexer, modified CSLA using D-Latch & Carry lookahead adders in 4-bit, 16-bit, 32-bit, are compared with the simulated results on the basis area.
2 citations
01 Nov 2014
TL;DR: A novel method to find a square root bit for every iteration, which hides the total delay of the multiplexer with dual path calculation is presented, and a new method uses the modified Most Significant Carry (MSC) generator, which determines the sign of each remainder faster than a carry lookahead adder, which reduces thetotal delay.
Abstract: This paper focuses on reducing the delay of the non-restoring square root algorithm. Although the non-restoring square root algorithm is faster than the other radix-2 digit recurrent square root algorithms, there are still some possibilities to enhance its performance. To improve its performance, two new approaches are proposed here. For the first proposed approach, a novel method to find a square root bit for every iteration, which hides the total delay of the multiplexer with dual path calculation is presented. Secondly, a new method uses the modified Most Significant Carry (MSC) generator, which determines the sign of each remainder faster than a carry lookahead adder, which reduces the total delay.
1 citations
01 Jan 2014
TL;DR: An enhanced 32-bit carry look- ahead(CLA) adder implementing using the constant delay (CD) logic, targeting at full-custom high-speed applications, with performance advantage over static and dynamic domino logic styles in a single-cycle multistage circuit block.
Abstract: This paper presents an enhanced 32-bit carry look- ahead(CLA) adder implementing using the constant delay (CD) logic, targeting at full-custom high-speed applications. The CD characteristic of this logic style regardless of the logic type makes it suitable in implementing complicated logic expressions such as addition. CD logic exhibits a unique characteristic where the output is pre-evaluated before the inputs from the preceding stage is ready. This feature offers performance advantage over static and dynamic domino logic styles in a single-cycle multistage circuit block. Several design considerations including timing window width adjustment and clock distribution are discussed. Using 65-nm general-purpose CMOS technology, the proposed logic demonstrates an average speed up of 94% and 56% over static and dynamic domino logic, respectively, in five different logic gates. Simulation results of 8-bit ripple carry adders show that CD logic is 39% and 23% faster than the static and dynamic-based adders, respectively. CD logic also demonstrates 39% speedup and 64%(22%) energy-delay product (EDP) reduction from static logic at 100% (10%) data activity in 32-bit carry look ahead adders. For 8-bit Wallace tree multiplier, CD logic achieves a similar speedup with at least 50% EDP reduction across all data activities.
Journal Article•
TL;DR: This paper simulates and synthesis different types of 16-bit sparse tree RSFQ adders using Xilinx ISE10.1i tool, and compares these three adders interms of LUT’s represents area) and delay values.
Abstract: In this paper, we propse 16-bit sparse tree RSFQ adder (Rapid single flux quantam), kogge-stone adder, carry lookahead adder. In general N-bit adders like Ripple carry adder s(slow adders compare to other adders), and carry lookahead adders(area consuming adders) are used in earlier days. But now the most of industries are using parallel prefix adders because of their advantages compare to kogge-stone adder, carry lookahead adder, Our prefix sparse tree adders are faster and area efficient. Parallel prefix adder is a technique for increasing the speed in DSP processor while performing addition. We simulate and synthesis different types of 16-bit sparse tree RSFQ adders using Xilinx ISE10.1i tool, By using these synthesis results, We noted the performance parameters like number of LUT’s and delay. We compare these three adders interms of LUT’s represents area) and delay values.
01 Jan 2014
TL;DR: The logic operations involved in conventional carry select adder (CSLA) and binary to excess-1 converter (BEC)-based CSLA with bent kung adder are analyzed to study the data dependence and to identify redundant logic operations.
Abstract: In Very Large Scale Integration (VLSI) designs, Parallel prefix adders (PPA) have the better delay perfor mance. This paper investigates four types of PPA’s (Kogge Stone Adder(KSA), Spanning Tree Adder (STA), Brent Kung Adder (BKA) and Sparse Kogge Stone Adder (SKA)). Additionally Ripple Carry Adder (RCA), Carry Lookahead Adder (CLA) and Carry Skip Adder (CSA) are also investigated. These adders are implemented in verilog Hardware Description Language (HDL) using Xilinx Integrated Software Environment (ISE) 13.2 Design Suite. These designs are implemented in Xilinx Virtex 5 Field Programmable Gate Arrays (FPGA) and delays are measured using Agilent 1692A logic analyzer and all these adder’s delay, power and area are investigated and compared finally.
01 Jan 2014
TL;DR: In this article, a modified self-resetting logic (SRL) technique was proposed to improve the performance of low power adder circuits using 120nm CMOS processing technology.
Abstract: 3 Abstract: Dynamic CMOS logic families are not an ideal option for low power circuits due to short circuit power dissipation, charge sharing and charge leakage. Self-Resetting Logic (SRL) has been widely preferred to overcome these issues; however it suffers from static power dissipation and low output voltage due to nMOS pull down network makes conductance overlap between nMOS and pMOS. This paper proposes a modified SRL technique which combines sleepy transistor and self-resetting logic to improve the performance of the high speed low power adder circuits. The proposed method is applied in different adder circuits and compared with existing SRL technique in terms of Average power dissipation, Power delay product and Energy delay product. Using modified SRL technique, carry lookahead adder and carry save adder are designed and implemented using 120nm CMOS processing technology. The obtained results show that the modified SRL technique is superior to existing techniques while considering speed and power dissipation of adder circuits.
Journal Article•
TL;DR: This paper simulates and synthesis different types of 16-bit sparse tree RSFQ adders using Xilinx ISE10.1i tool, and compares these three adders interms of LUT’s represents area) and delay values.
Abstract: In this paper, we propse 16-bit sparse tree RSFQ adder (Rapid single flux quantam), kogge-stone adder, carry lookahead adder. In general N-bit adders like Ripple carry adder s(slow adders compare to other adders), and carry lookahead adders(area consuming adders) are used in earlier days. But now the most of industries are using parallel prefix adders because of their advantages compare to kogge-stone adder, carry lookahead adder, Our prefix sparse tree adders are faster and area efficient. Parallel prefix adder is a technique for increasing the speed in DSP processor while performing addition. We simulate and synthesis different types of 16-bit sparse tree RSFQ adders using Xilinx ISE10.1i tool, By using these synthesis results, We noted the performance parameters like number of LUT’s and delay. We compare these three adders interms of LUT’s represents area) and delay values. Keywords—digital arithmetic, RSFQ adder, kogge-stone adder ,carry operator, prefix adder.
Journal Article•
TL;DR: Power consumption and delay of a 4-bit carry look ahead adder, implemented in static CMOS and adiabetic logic (ECRL) is analyzed.
Abstract: Now–a-days in digital circuit some important issues like high speed, high throughput, small silicon area, and low power consumption is being considered by designers. Full adders are important components in applications such as subtraction, counting, multiplication, filtering, digital signal processors (DSP) architectures and microprocessors. So for designer it is a great interest to design Carry-look ahead adder because of its high speed operation. In this paper power consumption and delay of a 4-bit carry look ahead adder, implemented in static CMOS and adiabetic logic (ECRL) is analyzed.