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Showing papers on "Carry-lookahead adder published in 2016"


Journal ArticleDOI
TL;DR: In this article, the implementation of an 8-bit multiplier design employing CMOS full adders, full adder using Double Pass Transistor (DPL) and multi-output carry Lookahead logic (CLA) is addressed.

32 citations


Proceedings ArticleDOI
20 May 2016
TL;DR: A novel architecture of Secure Hash Algorithm-1(SHA-1) for increased throughput and reduced area is presented and Carry Save Adder using Carry Lookahead Adder in its final stage is used for multi-input addition function to achieve high performance.
Abstract: In this work, a novel architecture of Secure Hash Algorithm-1(SHA-1) for increased throughput and reduced area is presented. Various acceleration techniques are applied such as pre-computation, loop unfolding, and pipelining simultaneously. Carry Save Adder using Carry Lookahead Adder in its final stage is used for multi-input addition function to achieve high performance. The proposed architecture is designed using VHDL language. The synthesis and simulation work is performed in Xilinx ISE Design Suite 13.2 tool. The present implementation of SHA-1 offers better results as compared to previous works.

8 citations


Posted Content
TL;DR: It is shown in this work that with improved section-carry based carry lookahead generators, the resulting SCBCLAs exhibit significant improvements in FOM, and the proposed optimized hybrid SCBCLA is still the winner and has a better FOM than the currently optimized hybrid CCLA.
Abstract: The section-carry based carry lookahead adder (SCBCLA) architecture was proposed as an efficient alternative to the conventional carry lookahead adder (CCLA) architecture for the physical implementation of computer arithmetic. In previous related works, self-timed SCBCLA architectures and synchronous SCBCLA architectures were realized using standard cells and FPGAs. In this work, we deal with improved realizations of synchronous SCBCLA architectures designed in a semi-custom fashion using standard cells. The improvement is quantified in terms of a figure of merit (FOM), where the FOM is defined as the inverse product of power, delay and area. Since power, delay and area of digital designs are desirable to be minimized, the FOM is desirable to be maximized. Starting from an efficient conventional carry lookahead generator, we show how an optimized section-carry based carry lookahead generator is realized. In comparison with our recent work dealing with standard cells based implementation of SCBCLAs to perform 32-bit addition of two binary operands, we show in this work that with improved section-carry based carry lookahead generators, the resulting SCBCLAs exhibit significant improvements in FOM. Compared to the earlier optimized hybrid SCBCLA, the proposed optimized hybrid SCBCLA improves the FOM by 88.3%. Even the optimized hybrid CCLA features improvement in FOM by 77.3% over the earlier optimized hybrid CCLA. However, the proposed optimized hybrid SCBCLA is still the winner and has a better FOM than the currently optimized hybrid CCLA by 15.3%. All the CCLAs and SCBCLAs are implemented to realize 32-bit dual-operand binary addition using a 32/28nm CMOS process.

5 citations


Posted Content
TL;DR: Based on the simulation results for 32-bit dual-operand addition obtained by targeting a high-end 32/28nm CMOS process, it is found that an optimized SCBCLA architecture reports a 9.8% improvement in figure-of-merit (FOM) compared to an optimized CCLA architecture, where the FOM is defined as the inverse of the product of power, delay, and area.
Abstract: The section-carry based carry lookahead adder (SCBCLA) topology was proposed as an improved high-speed alternative to the conventional carry lookahead adder (CCLA) topology in previous works. Self-timed and FPGA-based implementations of SCBCLAs and CCLAs were considered earlier, and it was found that SCBCLAs could help in delay reduction i.e. pave the way for improved speed compared to CCLAs at the expense of some increase in area and/or power parameters. In this work, we consider semi-custom ASIC-based implementations of different variants of SCBCLAs and CCLAs to perform 32-bit dual-operand addition. Based on the simulation results for 32-bit dual-operand addition obtained by targeting a high-end 32/28nm CMOS process, it is found that an optimized SCBCLA architecture reports a 9.8% improvement in figure-of-merit (FOM) compared to an optimized CCLA architecture, where the FOM is defined as the inverse of the product of power, delay, and area. It is generally inferred from the simulations that the SCBCLA architecture could be more beneficial compared to the CCLA architecture in terms of the design metrics whilst benefitting a variety of computer arithmetic operations involving dual-operand and/or multi-operand additions. Also, it is observed that heterogeneous CLA architectures tend to fare well compared to homogeneous CLA architectures, as substantiated by the simulation results.

4 citations



Patent
17 Feb 2016
TL;DR: In this article, a 64-bit fixed-point arithmetic logical unit (arithmetic logical unit) circuit based on a three-stage carry lookahead adder in a GPDSP was proposed.
Abstract: The invention relates to a 64-bit fixed-point ALU (arithmetic logical unit) circuit based on a three-stage carry lookahead adder in a GPDSP. The 64-bit fixed-point ALU circuit comprises an ALU decoding station, an inter-station register, a universal register RF and an execution station, wherein the ALU decoding station receives an instruction signal of a distribution module, sends out a read signal and a read address to the universal register RF through decoding logics, and reads an original operand; the execution station receives the original operand which is sent to a calculation core of an IALU to be calculated with an instruction selection signal and a control signal generated through decoding after passing through preprocessing logics; after the calculation is completed, a write signal, a write address and write data are sent to the universal register RF or other registers; the execution station realizes all instructions except a saturation instruction and an LZD instruction through the 64-bit three-stage carry lookahead adder, and performs distinguished control through the control signal. The 64-bit fixed-point ALU circuit has the advantages that the area expenditure can be reduced; selectors can be reduced; the time sequence can be reduced, and the like.

1 citations


DOI
01 Mar 2016
TL;DR: This project proposes to design hybrid carry select adders involving carry select and carry look-ahead adders with and without ripple carry adder (RCA) using very high speed integrated circuits hardware description language (VHDL).
Abstract: Carry select adder (CSA) is a square-root time high-speed adder. CSA is one of the fastest adders used in many data processing systems to perform fast arithmetic operations. In this project we propose to design hybrid carry select adders with a focus on high speed. CSA is a compromise between the longer delay Ripple carry adder (RCA) and the shorter delay Carry look-ahead adder (CLA). Conventionally carry select adders are realize using the full adders and 2:1 multiplexers. On the other hand hybrid carry select adders involve a combination of carry select and carry look-ahead adders.In this work, we propose to design hybrid carry select adders involving carry select and carry look-ahead adders with and without ripple carry adder (RCA) using very high speed integrated circuits hardware description language (VHDL). Keywords— Carry select adder, Ripple carry adder, Carry lookahead adder, VHDL code

Journal Article
TL;DR: In this article, the authors present an all-optical implementa-tion of a digital multiplexer using MZI switches, where both non-reversible and reversible verifications of the design are proposed, along with analytical evaluation of the complexity both in terms of delay and resource requirements.
Abstract: With the advancements in semiconductor technology, there has been an increased emphasis in low-power design techniques over the last few decades. Now-a-days, semiconductor optical amplifier (SOA)- based Mach–Zehnder interferometer (MZI) plays a vital role in the field of ultra-fast all-optical signal processing. Reversible computing has been proposed by several researchers as a possible alternative to address the energy dissipation problem. Several implementation alternatives for reversible logic circuits have also been explored in recent years, like adiabatic logic, nuclear magnetic resonance, optical computing, etc. Recently researchers have proposed implementations of vari­ous reversible logic circuits in the all-optical computing domain. Most of these works are based on semicon­ductor optical amplifier (SOA) based Mach-Zehnder in­terferometer (MZI), which provides desirable features like low power, fast switching and ease of fabrication. In this paper we present an all-optical implementa­tion of a digital multiplexer using MZI switches.we ex­ploring this project with MZI based Carry lookahead Adder(CLA). Both non-reversible and reversible ver­sions of multiplexer design are proposed, along with analytical evaluation of the design complexities both in terms of delay and resource requirements. The final optical netlists obtained have been compared against traditional reversible synthesis approaches, by using an available synthesis tool and then mapping the revers­ible gates to MZI switch based implementations. Some techniques for optimizing the final optical netlists have also been proposed.

Journal ArticleDOI
01 Jan 2016
TL;DR: In order to improve the speed performance with lower hardware cost, this paper presents a simple and modular hybrid adders with the proposed UCA concept, where the hybrid adder takes the lower-bit carry lookahead adder as a module and many of the CLA modules are serially connected in a fashion similar to the RCA.
Abstract: Constant multiplier performs a multiplication of a data-input with a constant value. Constant multipliers are essential components in various types of arithmetic circuits, such as filters in digital signal processor (DSP) units and they are prevalent in modern VLSI designs. This study presents efficient algorithms and their fast hardware implementation for performing multiplying-by-(2k?±?1), or (2k?±?1)N, operation with additions. No multiplications are needed. The value of (2k?±?1)N can be computed by adding (±N) to its k-bits left-shifted value 2kN. The additions can be performed by the full-adder-based (FA-based) ripple carry adder (RCA) for simple architecture. This paper presents the unit cells for additions (UCAs). Results show that the UCA-based RCA achieves 34 % faster than the FA-based RCA. Further, in order to improve the speed performance with lower hardware cost, this paper also presents a simple and modular hybrid adder with the proposed UCA concept, where the hybrid adder takes the lower-bit carry lookahead adder (CLA) as a module and many of the CLA modules are serially connected in a fashion similar to the RCA. Results show that the proposed hybrid adder achieved speed performance improvement while maintaining its modular and regular structure.

Patent
22 Dec 2016
TL;DR: In this article, the mixed-radix carry-lookahead adder is described, where each stage may be of a different radix and each stage operates on input bits, creating and implementing propagate and generate signals for each bit.
Abstract: Embodiments described herein are directed to mixed-radix carry-lookahead adders and methods performed thereby. The mixed-radix carry-lookahead adder includes an multiple carry-lookahead stages, where each stage may be of a different radix. Each stage operates on input bits, creating and implementing propagate and generate signals for each bit. The carry-lookahead stages also compute an XOR of the inputs that is forwarded to a final carry-lookahead stage. The elements of the initial and subsequent carry-lookahead stages are arranged such that each of the propagate and generate output signals passes through a minimal number of passive transmission lines. The final stage of the mixed-radix carry-lookahead adder includes an XOR logic gate configured to receive the generate output from an intermediate carry-lookahead stage and XOR the generate output received from the intermediate carry-lookahead stage with the computed XOR signal forwarded from the initial carry-lookahead stage to produce a sum of the input bits.