Showing papers on "Carry-lookahead adder published in 2017"

Carbon nanotube FET-based low-delay and low-power multi-digit adder designs

Abstract: Several field-effect transistor (FET)-based device technologies are emerging as powerful alternatives to the classical metal oxide semiconductor FET (MOSFET) for computing applications. The focus of this study is on arithmetic circuit design in carbon nanotube FET (CNTFET) technology. In particular, the authors develop low-delay and low-power multi-ternary digit CNTFET-based adder designs. The proposed designs are based on unary operators of multi-valued logic. Efficient designs for primitives such as ternary half-adder (HA) and full-adder are developed and they are used to obtain low-complexity multi-digit adders based on the notions of conditional sum and carry lookahead. Extensive HSPICE simulations reveal that the power-delay product of the proposed CNTFET-based HA and full-adder are roughly 20 and 50%, respectively, of that of recent designs. Further, the proposed CNTFET-based conditional sum adder has a power-delay product of approximately 27% of that of a multi-trit design derived from a recent single-trit adder design (for a load capacitance of 2 fF). Moreover, the proposed CNTFET-based carry lookahead adder has low delay in comparison with the conditional sum strategy for different supply voltages. Studies on robustness of the designs are also reported.

Efficient implementation of adder circuits in memristive crossbar array

Abstract: Memristor is a two terminal passive circuit element that can be used in non-volatile storage applications. In addition, memristor can also be used to implement logic functions. This paper presents the design of adder circuits in memristor crossbar. We have used the MAGIC design style to implement the gates required for the adder circuits. The implementation is based on in-memory computing where the input data is assumed to be stored in the crossbar, and the processing is done in the storage unit itself. We have estimated the gate delay and switching energy using SPICE simulation under Cadence Virtuoso environment. We have evaluated the latency of the half adder, full adder, 4-bit ripple carry, 4-bit carry lookahead adder and generalized the latency and area estimates for an n-bit ripple-carry adder. The proposed method is compared with an alternate memristor based synthesis method (viz. IMPLY) and is found to be more efficient in terms of latency and energy with similar area overheads.

Design and implementation of high speed modified booth multiplier using hybrid adder

Abstract: Multiplier is one of the most desirable component in most of the processors designed today The speed of multiplier determines the speed of the processor So there is a need of high speed multiplier In this paper, a novel method for Multiplication is proposed by combining Modified Booth algorithm, Wallace tree architecture and Hybrid adder design Modified Booth Multiplier reduces the number of partial products and has least latency as compared to other multiplier designs Wallace Tree increases the speed by parallel addition of partial products Adders play an important role in addition of partial products If the speed at which the addition operation is performed is increased than the overall speed of the multiplier design will increase So the main focus in this paper is to increase the speed of the adder A novel hybrid adder design is used in the multiplier design which, has less delay and occupies less area Area, delay and power complexities of the proposed Multiplier design are reported The proposed Modified Booth Multiplier design shows better performance compare to conventional method using Carry LookAhead Adder and has advantages of reduced area overhead and critical path delay The proposed multiplier design has been synthesized using Xilinx ISE 101 design tool and simulated using ModelSim157g The programming language used is Verilog HDL

Latency Optimized Asynchronous Early Output Ripple Carry Adder Based on Delay-insensitive Dual-rail Data Encoding

Abstract: Asynchronous circuits employing delay-insensitive codes for data representation i.e. encoding and following a 4-phase return-to-zero protocol for handshaking are generally robust. Depending upon whether a single delay-insensitive code or multiple delay-insensitive code(s) are used for data encoding, the encoding scheme is called homogeneous or heterogeneous delay-insensitive data encoding. This article proposes a new latency optimized early output asynchronous ripple carry adder (RCA) that utilizes single-bit asynchronous full adders (SAFAs) and dual-bit asynchronous full adders (DAFAs) which incorporate redundant logic and are based on the delay-insensitive dual-rail code i.e. homogeneous data encoding, and follow a 4-phase return-to-zero handshaking. Amongst various RCA, carry lookahead adder (CLA), and carry select adder (CSLA) designs, which are based on homogeneous or heterogeneous delay-insensitive data encodings which correspond to the weak-indication or the early output timing model, the proposed early output asynchronous RCA that incorporates SAFAs and DAFAs with redundant logic is found to result in reduced latency for a dual-operand addition operation. In particular, for a 32-bit asynchronous RCA, utilizing 15 stages of DAFAs and 2 stages of SAFAs leads to reduced latency. The theoretical worst-case latencies of the different asynchronous adders were calculated by taking into account the typical gate delays of a 32/28nm CMOS digital cell library, and a comparison is made with their practical worst-case latencies estimated. The theoretical and practical worst-case latencies show a close correlation....

Asynchronous early output section-carry based carry lookahead adder with alias carry logic

Abstract: A new asynchronous early output section-carry based carry lookahead adder (SCBCLA) with alias carry output logic is presented in this paper. To evaluate the proposed SCBCLA with alias carry logic and to make a comparison with other CLAs, a 32-bit addition operation is considered. Compared to the weak-indication SCBCLA with alias logic, the proposed early output SCBCLA with alias logic reports a 13% reduction in area without any increases in latency and power dissipation. On the other hand, in comparison with the early output recursive CLA (RCLA), the proposed early output SCBCLA with alias logic reports a 16% reduction in latency while occupying almost the same area and dissipating almost the same average power. All the asynchronous CLAs are quasi-delay-insensitive designs which incorporate the delay-insensitive dual-rail data encoding and adhere to the 4-phase return-to-zero handshaking. The adders were realized and the simulations were performed based on a 32/28nm CMOS process.

Asynchronous Early Output Section-Carry Based Carry Lookahead Adder with Alias Carry Logic

Abstract: A new asynchronous early output section-carry based carry lookahead adder (SCBCLA) with alias carry output logic is presented in this paper. To evaluate the proposed SCBCLA with alias carry logic and to make a comparison with other CLAs, a 32-bit addition operation is considered. Compared to the weak-indication SCBCLA with alias logic, the proposed early output SCBCLA with alias logic reports a 13% reduction in area without any increases in latency and power dissipation. On the other hand, in comparison with the early output recursive CLA (RCLA), the proposed early output SCBCLA with alias logic reports a 16% reduction in latency while occupying almost the same area and dissipating almost the same average power. All the asynchronous CLAs are quasi-delay-insensitive designs which incorporate the delay-insensitive dual-rail data encoding and adhere to the 4-phase return-to-zero handshaking. The adders were realized and the simulations were performed based on a 32/28nm CMOS process.

A Novel Nanometric Parity-Preserving Reversible Carry-Lookahead Adder

Abstract: During recent years, reversible logic received important attention in cryptography, optical processing, quantum computing, and nanotechnology. Among the reversible computation units, the adder unit is considered the most fundamental computation unit to build a quantum computing system. Due to its low latency, the reversible carry-lookahead adder is mostly used and considered. Parity preserving is also one of the oldest methods for error recognition in digital systems. In this article, we offer new proposals for the nanometric parity-preserving reversible 2-bit carry-lookahead adder. Compared with previous designs, we will demonstrate that our designs would be optimal in the number of garbage outputs, constant inputs, and quantum costs. In order to design circuits at a higher level, we also offer new proposals for the nanometric parity-preserving reversible 4-bit carry-lookahead adder. Since previous proposals that were presented as 4-bit did not have the reversible parity-preserving property, we p...

A quick automatic frequency calibration circuit for radio frequency phase -locked loop

Abstract: The utility model relates to a quick automatic frequency calibration circuit for radio frequency phase -locked loop can make the radio frequency phase -locked loop that adopts this circuit cover great output bandwidth under lower voltage -controlled gain condition, possesses very fast locking speed simultaneously. This circuit adopts accurate loop configuration, including a voltage comparater, a pulse generation ware and a counter module, has simple structure, the fast characteristics of locking. The counter module uses binary search method and carry lookahead adder further to shorten the phase -locked loop frequency coarse adjustment time to the locking process accelerates.

Latency Optimized Asynchronous Early Output Ripple Carry Adder based on Delay-Insensitive Dual-Rail Data Encoding

Abstract: Asynchronous circuits employing delay-insensitive codes for data representation i.e. encoding and following a 4-phase return-to-zero protocol for handshaking are generally robust. Depending upon whether a single delay-insensitive code or multiple delay-insensitive code(s) are used for data encoding, the encoding scheme is called homogeneous or heterogeneous delay-insensitive data encoding. This article proposes a new latency optimized early output asynchronous ripple carry adder (RCA) that utilizes single-bit asynchronous full adders (SAFAs) and dual-bit asynchronous full adders (DAFAs) which incorporate redundant logic and are based on the delay-insensitive dual-rail code i.e. homogeneous data encoding, and follow a 4-phase return-to-zero handshaking. Amongst various RCA, carry lookahead adder (CLA), and carry select adder (CSLA) designs, which are based on homogeneous or heterogeneous delay-insensitive data encodings which correspond to the weak-indication or the early output timing model, the proposed early output asynchronous RCA that incorporates SAFAs and DAFAs with redundant logic is found to result in reduced latency for a dual-operand addition operation. In particular, for a 32-bit asynchronous RCA, utilizing 15 stages of DAFAs and 2 stages of SAFAs leads to reduced latency. The theoretical worst-case latencies of the different asynchronous adders were calculated by taking into account the typical gate delays of a 32/28nm CMOS digital cell library, and a comparison is made with their practical worst-case latencies estimated. The theoretical and practical worst-case latencies show a close correlation....

A 0.2V 2.3pJ/Cycle 28dB output SNR hybrid Markov random field probabilistic-based circuit for noise immunity and energy efficiency

Abstract: In this paper, two kinds of simplified cell structures for low voltage noise immunity and a hybrid Markov Random Field probabilistic-based circuit design technique are proposed to reduce the hardware overhead and improve the noise immunity. To demonstrate the proposed technique, four kinds of test chips with an 8-bit carry lookahead adder (CLA) are fabricated in a 130nm CMOS technology. Measurement results show the proposed hybrid MRF CLA improves 14% noise immunity, saves 53% energy consumption and reduces 11% circuit area than the other CLAs.

Design of high performance double precision hybrid ALU for SoC applications

Abstract: In this paper, we have presented a design of hybrid arithmetic logic unit (ALU) in Double precision format (DPF) according to the IEEE-754 standard. In this we have designed an ALU which consists of the two different architectures. First architecture is semi-floating point unit (Semi-FPU) and the second architecture is floating point unit (FPU). Semi-FPU takes a 32-bit integer input and produces an output in 64-bit DPF. And the floating point unit takes the input in 64-bit DPF and produces the output in 64-bit DPF. FPU also provides rounding and exception handling. Both the architectures can perform addition, subtraction, division, and multiplication. ALU is designed with three different adders which is ripple carry adder, carry lookahead adder, and carry save adder. The parameters such as area, power, and delay is compared for each modules (add, mul, div) of ALU with all three different adders. And according to the power-delay product, the best adder among the above three is chosen for each operation. The sub modules are written in Verilog HDL. For simulation we have used Xilinx ISE software and synthesis is done using cadence Encounter RTL compiler using typical libraries of TSMC 45 nm technology.