Showing papers on "Carry-lookahead adder published in 2019"

A Carry Lookahead Adder Based on Hybrid CMOS-Memristor Logic Circuit

Abstract: Memristor-based digital logic circuits open new pathways for exploring advanced computing architectures, which provide a promising alternative to conventional IC technology In several memristor-based logic design methods, the memristor ratioed logic (MRL) is compatible with traditional CMOS technology Two kinds of carry-lookahead adders (CLA) based on the hybrid CMOS-memristor structure are proposed, within which one is based on MRL logic, and the other is an improved one that is implemented by MRL universal gate (MRLUG) The proposed CLAs are verified by theoretical analyses and simulations, showing that the proposed design method requires fewer memristors and CMOSs than the IMP-based or CMOS-based CLAs, which means smaller circuit size and lower power consumption

Design and Performance Comparison among Various types of Adder Topologies

Abstract: In the area of Very Large Scale Integration (VLSI) design, summing circuits are one of the most widely used entities in processor data path architecture. With the advances in VLSI technology, research works are emerging on to design an architecture with low power consumption, high speed, less area or the combination of them. In this paper, we have presented the implementation of various 16bit adder architectures of Ripple Carry Adder (RCA), Carry Lookahead Adder (CLA) and Carry Skip Adder (CSA)) and also including parallel prefix adders like Spanning Tree Adder (STA), Kogge Stone Adder (KSA), Sparse Kogge Stone Adder (SKA) and Brent Kung Adder (BKA).The comparative analysis of different adders has performed with respect to the performance parameters – area, delay and power. All adder designs have been simulated, synthesized and implemented on Xilinx Virtex-7 board using Xilinx ISE 2014.7 design tool. Programming language used is Verilog HDL.

N-digits Ternary Carry Lookahead Adder Design

Abstract: Carry lookahead adders (CLAs) are extensively used in digital circuits due to their logarithmic computational time (O(log n)) compared to linear computational time(O(n)) in the ripple carry adders. In this paper, two design approaches for N-digits ternary logic CLA based on K-map and threshold logic methods are proposed in addtion to their realization using CNTFETs only and memristor with CNTFETs. Finally, 4-bit ternary CLA is presented. A comparison and tradeoffs among the proposed designs are presented in terms of the delay and the area. The comparison shows that the transistor-only-based implementation is the best choice in the K-map design approach. However, the memristor and transistor-based implementation based on memristor and transistors integration is the best in the threshold logic (TL) design. Therefore, the proposed designs are very promising to build high performance full ternary ALU unit.

Factorized Carry Lookahead Adders

Abstract: New factorized carry lookahead adders corresponding to the regular carry lookahead adder (RCLA) architecture viz. the factorized regular carry lookahead adder (FRCLA), and the block carry lookahead adder (BCLA) architecture viz. the factorized block carry lookahead adder (FBCLA) are presented. The idea behind the proposed factorized carry lookahead adders is discussed and example implementations are provided. The RCLA, BCLA, FRCLA and FBCLA were realized using the gates of a 32/28nm CMOS standard digital cell library. The results show that the proposed FRCLA achieves an average reduction in the power-delay product i.e., energy by 7.85% for 32- and 64-bit additions compared to the best among the rest.

Speed and energy optimized quasi-delay-insensitive block carry lookahead adder.

Abstract: We present a new asynchronous quasi-delay-insensitive (QDI) block carry lookahead adder with redundant carry (BCLARC) realized using delay-insensitive dual-rail data encoding and 4-phase return-to-zero (RTZ) and 4-phase return-to-one (RTO) handshaking. The proposed QDI BCLARC is found to be faster and energy-efficient than the existing asynchronous adders which are QDI and non-QDI (i.e., relative-timed). Compared to existing asynchronous adders corresponding to various architectures such as the ripple carry adder (RCA), the conventional carry lookahead adder (CCLA), the carry select adder (CSLA), the BCLARC, and the hybrid BCLARC-RCA, the proposed BCLARC is found to be faster and more energy-optimized. The cycle time (CT), which is expressed as the sum of the worst-case times taken for processing the data and the spacer, governs the speed. The product of average power dissipation and CT viz. the power-cycle time product (PCTP) defines the low power/energy efficiency. For a 32-bit addition, the proposed QDI BCLARC achieves the following reductions in design metrics on average over its counterparts when considering RTZ and RTO handshaking: i) 20.5% and 19.6% reductions in CT and PCTP respectively compared to an optimum QDI early output RCA, ii) 16.5% and 15.8% reductions in CT and PCTP respectively compared to an optimum relative-timed RCA, iii) 32.9% and 35.9% reductions in CT and PCTP respectively compared to an optimum uniform input-partitioned QDI early output CSLA, iv) 47.5% and 47.2% reductions in CT and PCTP respectively compared to an optimum QDI early output CCLA, v) 14.2% and 27.3% reductions in CT and PCTP respectively compared to an optimum QDI early output BCLARC, and vi) 12.2% and 11.6% reductions in CT and PCTP respectively compared to an optimum QDI early output hybrid BCLARC-RCA. The adders were implemented using a 32/28nm CMOS technology.

Speed and Energy Optimised Quasi-Delay-Insensitive Block Carry Lookahead Adder

Abstract: We present a new asynchronous quasi-delay-insensitive (QDI) block carry lookahead adder with redundancy carry (BCLARC) realized using delay-insensitive dual-rail data encoding and 4-phase return-to-zero (RTZ) and 4-phase return-to-one (RTO) handshaking. The proposed QDI BCLARC is found to be faster and energy-efficient than the existing asynchronous adders which are QDI and non-QDI (i.e., relative-timed). Compared to existing asynchronous adders corresponding to various architectures such as ripple carry adder (RCA), conventional carry lookahead adder (CCLA), carry select adder (CSLA), BCLARC, and hybrid BCLARC-RCA, the proposed BCLARC is found to be faster and more energy-optimised. The cycle time (CT), which is the sum of forward and reverse latencies, governs the speed; and the product of average power dissipation and cycle time viz. the power-cycle time product (PCTP) defines the low power/energy efficiency. For a 32-bit addition, the proposed QDI BCLARC achieves the following average reductions in design metrics over its counterparts when considering RTZ and RTO handshaking: i) 20.5% and 19.6% reductions in CT and PCTP respectively compared to an optimum QDI early output RCA, ii) 16.5% and 15.8% reductions in CT and PCTP respectively compared to an optimum relative-timed RCA, iii) 32.9% and 35.9% reductions in CT and PCTP respectively compared to an optimum uniform input-partitioned QDI early output CSLA, iv) 47.5% and 47.2% reductions in CT and PCTP respectively compared to an optimum QDI early output CCLA, v) 14.2% and 27.3% reductions in CT and PCTP respectively compared to an optimum QDI early output BCLARC, and vi) 12.2% and 11.6% reductions in CT and PCTP respectively compared to an optimum QDI early output hybrid BCLARC-RCA. The adders were implemented using a 32/28nm CMOS technology.

High-precision multi-channel time-to-digital converter

Abstract: The invention discloses a high-precision multi-channel time-to-digital converter (TDC) The time-to-digital converter adopts a two-stage structure; the first-stage structure adopts a pulse counting type time-to-digital converter based on a carry lookahead adder, and is used for achieving a high working frequency and a wide dynamic range; and the second-stage structure adopts a multi-channel time-to-digital converter based on a voltage-controlled differential time delay unit and a true single phase clocked trigger, and the second-stage structure is used for improving the measurement precision and reducing the measurement error According to the product, the principle of two-stage measurement is utilized, so that the dynamic range and the resolution ratio are taken into consideration A voltage-controlled differential phase inverter and the true single phase clocked (TSPC) trigger are used in the second-stage TDC, so that good linearity and low error rate of a system are ensured; and meanwhile, an integral framework adopts a three-channel structure, so that the length of a single time delay chain is reduced by 2/3, the uncertainty is reduced by 43%, and the performance of the systemis effectively improved

Method for realizing four-bit carry lookahead adder circuit based on DNA strand displacement

Abstract: The invention provides a method for realizing a four-bit carry lookahead adder circuit based on DNA strand displacement, which comprises the following steps: researching a DNA strand displacement reaction principle based on DNA strand displacement reaction, designing a model based on DNA strand displacement, realizing logic exclusive-OR operation, and designing a biogenic circuit model on the basis of the logic exclusive-OR operation; designing a biochemical circuit of a four-bit carry lookahead adder based on a biochemical logic gate, and using Visual DSD software for carrying out simulationanalysis on the logic circuit. The carry bits of all the bits in the four-bit carry lookahead adder are generated at the same time and do not influence one another, and although the circuit structureis complex, the operation speed is higher. According to the invention, the dynamic behavior of the logic circuit of the four-bit carry lookahead adder is verified, and the reasonability and effectiveness of the circuit are proved. A basic theoretical basis is provided for constructing a more complex logic operation circuit in the future, and the development of the biological computer is promoted,so that the reliability of the logic circuit of the biological computer is improved.

Design and Analysis of FinFET Based CSCPAL Low Power Adder

Abstract: An energy efficient and novel Charge Sharing Complementary Pass Transistor Adiabatic Logic (CSCPAL) operated by four phase power clock is proposed. It realizes low switching noise and incurs low leakage power. FinFETs are ideal devices for low power circuit design due to their enhanced properties of reduced short channel effects and lower leakage current. The circuits are designed using 32nm FinFET models and are simulated using Cadence® Virtuoso design tools. Efficiency of FinFET based CSCPAL is compared with FinFET based 2N2N2P, 2N2P and PFAL designs found in the literature. Energy consumption of CSCPAL Inverter/Buffer, AND and XOR sub modules used in the design of 8-bit Carry Lookahead Adder circuits have been compared with the 2N2P, 2N2N2P and PFAL based circuit counterparts. 8-bit CLA is taken as a benchmark circuit for validation of energy efficiency.

Delay Efficient All Optical Carry Lookahead Adder.

Abstract: Carry look ahead adders (CLA) are the fastest of all adders and achieve high speed through parallel carry computations. This method does not require the carry signal to propagate stage by stage. In this paper, an efficient all-optical realization of CLA is proposed using Mach–Zehnder interferometer (MZI) gates. Experimental results confirm the efficacy of the proposed design over similar existing designs.