Showing papers on "Carry-lookahead adder published in 2020"

Memristor-CNTFET based Ternary Full Adders

Abstract: Recently multilevel systems are one of the hottest topics in the digital electronics field. Multi-level logic (MVL) overcomes the issues of interconnections. The ternary system is a promising system where the implementation complexity is low and more information can be stored compared to the binary logic system. In this paper, 4-bit adder has been implemented with CNTFETs and memristors using three different methods; carry-ripple adder, carry-skip adder and carry-lookahead adder. A comparative study between the three adders is introduced in terms of the average power and delay. The adders have been validated with SPICE simulations using VTEAM memristor and Stanford CNTFET transistor models. The carry-lookahead adder (CLA) shows 10x better power-delay product compared to carry ripple and carry-skip adders. The power and temperature variations are studied on the designed circuits.

Efficient Construction of a Control Modular Adder on a Carry-Lookahead Adder Using Relative-phase Toffoli Gates

Abstract: Control modular addition is a core arithmetic function, and we must consider the computational cost for actual quantum computers to realize efficient implementation. To achieve a low computational cost in a control modular adder, we focus on minimizing KQ, defined by the product of the number of qubits and the depth of the circuit. In this paper, we construct an efficient control modular adder with small KQ by using relative-phase Toffoli gates in two major types of quantum computers: Fault-Tolerant Quantum Computers (FTQ) on the Logical layer and Noisy Intermediate-Scale Quantum Computers (NISQ). We give a more efficient construction compared to Van Meter and Itoh's, based on a carry-lookahead adder. In FTQ, $T$ gates incur heavy cost due to distillation, which fabricates ancilla for running $T$ gates with high accuracy but consumes a lot of specially prepared ancilla qubits and a lot of time. Thus, we must reduce the number of $T$ gates. We propose a new control modular adder that uses only 20% of the number of $T$ gates of the original. Moreover, when we take distillation into consideration, we find that we minimize $\text{KQ}_{T}$ (the product of the number of qubits and $T$-depth) by running $\Theta\left(n / \sqrt{\log n} \right)$ $T$ gates simultaneously. In NISQ, CNOT gates are the major error source. We propose a new control modular adder that uses only 35% of the number of CNOT gates of the original. Moreover, we show that the $\text{KQ}_{\text{CX}}$ (the product of the number of qubits and CNOT-depth) of our circuit is 38% of the original. Thus, we realize an efficient control modular adder, improving prospects for the efficient execution of arithmetic in quantum computers.

Analysis of 8-bit Vedic Multiplier using high speed CLA Adder

Abstract: This research work proposes the vedic multiplier architecture with different carry lookahead adders like regular carry lookahead adder (RCLA), block carry lookahead adder (BCLA), factorized regular carry lookahead adder (FRCLA), factorized block carry lookahead adder (FBCLA). The vedic multipliers architecture was designed using ModelSim-Altera 6.3g (Quartus II 8.1) Web Edition and synthesized using Xilinx ISE Design suite. Initially the vedic multiplier was implemented using regular carry lookahead adder and replaced with other adders and the synthesis parameters were compared. After the comparison we have obsereved that the FRCLA is the best one interms of area and BCLA is the best one interms of delay.

T-count and Qubit Optimized Quantum Circuit Designs of Carry Lookahead Adder.

Abstract: Quantum circuits of arithmetic operations such as addition are needed to implement quantum algorithms in hardware. Quantum circuits based on Clifford+T gates are used as they can be made tolerant to noise. The tradeoff of gaining fault tolerance from using Clifford+T gates and error correcting codes is the high implementation overhead of the T gate. As a result, the T-count performance measure has become important in quantum circuit design. Due to noise, the risk for errors in a quantum circuit computation increases as the number of gate layers (or depth) in the circuit increases. As a result, low depth circuits such as quantum carry lookahead adders (QCLA)s have caught the attention of researchers. This work presents two QCLA designs each optimized with emphasis on T-count or qubit cost respectively. In-place and out-of-place versions of each design are shown. The proposed QCLAs are compared against the existing works in terms of T-count. The proposed QCLAs for out-of-place addition achieve average T gate savings of $54.34 \%$ and $37.21 \%$, respectively. The proposed QCLAs for in-place addition achieve average T gate savings of $72.11 \%$ and $35.87 \%$

Study of Different Adders Using Full Swing Gate Diffusion Input

Abstract: This paper presents the comparison of Multiple 16 Bit Adders using Gate Diffusion Input (GDI) and CMOS logic. Performance enhancements using Swing Restoration has been studied. The paper focuses on three commonly used adders: Ripple Carry Adder, Carry Select Adder and the Carry Lookahead Adder. The simulation results reveal smaller area and better consumption for the GDI logic when compared with their CMOS designs at 180nm GPDK Technologies. The results have been evaluated using spectre in Cadence Virtuoso IC614. For Ripple carry adder and carry Select adder the GDI logic out performs the CMOS logic in terms of area and power. However, CMOS shows better performance in terms of delay and Rise/Fall time. For Carry lookahead adder, GDI performs better in terms of area, while CMOS performs better in terms of power, delay and Rise/Fall Time.)

2D- Discrete Cosine Transform based Dynamically Controllable Image Compression Technique

Abstract: The Discrete Cosine Transform (DCT) is commonly used for the compression of images due to its property of high power compaction Multiplication is a key fundamental stage in the computation of Discrete Cosine Transform (DCT) of an image In this paper, a novel low-power, high-speed run-time configurable image compression technique based on 2D-Discrete Cosine Transform (DCT) and conventional carry lookahead adder is proposed In the proposed implementation of 2D-DCT using configurable booth multiplier, tuning of accuracy and the size of the compressed image is realized by masking the carry propagation of configurable adder at runtime We also calculated the various performance metrics such as Mean Square Error (MSE) and Peak Signal to Noise Ratio (PSNR) of conventional multiplier based 2D-DCT and proposed designs