Showing papers on "Carry-lookahead adder published in 2021"
TL;DR: Two QCLA designs each optimized with emphasis on T-count and T-depth or qubit cost, respectively are presented, each of which achieves T- depth savings ranging from 33.33% to 95.56% compared to existing works.
17 citations
07 Apr 2021
TL;DR: In this paper, an approximate carry-lookahead adder (ACLA) is proposed which makes use of an intelligent approach for judging the carry of subsequent stages and a correction mechanism is proposed so as to hinder substantial accuracy loss.
Abstract: Approximate computing in recent times has emerged as a popular alternative to conventional computing techniques. Fault-tolerant applications in the domains of machine learning, signal processing, and computer vision have shown promising results using approximate computing. Approximations on adders and multipliers have been widely proposed in literature and innovations on that front are still a necessity so as to target specific applications. In this paper, an approximate carry-lookahead adder (ACLA) is proposed which makes use of an intelligent approach for judging the carry of subsequent stages. Also, a correction mechanism is proposed so as to hinder substantial accuracy loss. Experimental results show that ACLA is faster than the traditional ripple-carry adder by 70.5% for 32-bit configurations on an average. In terms of accuracy, for 32-bit configurations, ACLA outperforms other state-of-the-art adders such as SARA [1] and BCSA [2] by 51%.
1 citations
02 Apr 2021
TL;DR: Radix-2 multiplier & pipeline feedforward-cutset-free carry-lookahead adder are used to enhance the traditional FDP unit and Pipeline concept is also infused into system to get the desired pipeline fused floating-point dot product (PFFDP) operations.
Abstract: Fused floating point operations play a major role in many DSP applications to reduce operational area & power consumption. Radix-2r multiplier (using 7-bit encoder technique) & pipeline feedforward-cutset-free carry-lookahead adder(PFCF-CLA) are used to enhance the traditional FDP unit. Pipeline concept is also infused into system to get the desired pipeline fused floating-point dot product (PFFDP) operations. Synthesis results are obtained using 60nm standard library with 1GHz clock. Power consumption of single & double precision operations are 2.24mW & 3.67mW respectively. The die areas are 27.48 mm2 , 46.72mm2 with an execution time of 1.91 ns , 2.07 ns for a single & double precision operations respectively. Comparison with previous data has also been performed. The area-delay product(ADP) & power-delay product(PDP) of our proposed architecture are 18%,22% & 27%,18% for single and double precision operations respectively.