Carry-lookahead adder

About: Carry-lookahead adder is a research topic. Over the lifetime, 243 publications have been published within this topic receiving 3794 citations.

Circuit design for a measurement-based quantum carry-lookahead adder

Abstract: We present the design and evaluation of a quantum carry-lookahead adder (QCLA) using measurement-based quantum computation (MBQC), called MBQCLA. QCLA was originally designed for an abstract, concurrent architecture supporting long-distance communication, but most realistic architectures heavily constrain communication distances. The quantum carry-lookahead adder is faster than a quantum ripple-carry adder; QCLA has logarithmic depth while ripple adders have linear depth. MBQCLA utilizes MBQC's ability to transfer quantum states in unit time to accelerate addition. MBQCLA breaks the latency limit of addition circuits in nearest neighbor-only architectures: compared to the Θ(n) limit on circuit depth for linear nearest-neighbor architectures, it can reach Θ(log n) depth. MBQCLA is an order of magnitude faster than a ripple-carry adder when adding registers longer than 100 qubits, but requires a cluster state that is an order of magnitude larger. The cluster state resources can be classified as computation ...

A fast hybrid carry-lookahead/carry-select adder design

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VLSI design of a quaternary multiplier with direct generation of partial products

Abstract: This paper presents the VLSI design of a novel quaternary multiplier with direct generation of partial products using a radix-4 redundant number system. The structure of the multiplier is so simple and regular that it is suitable for VLSI implementation. Partial products in the multiplier are generated as the corresponding value 0 to 9 and are implemented by simple CMOS current-mode circuits. To add partial products in the multiplier, we introduce a redundant multi-valued adder (RMA). The RMA can add two redundant numbers without carry propagation. The resulting numbers in the final level of additions are also redundant. We use a high speed quaternary carry-lookahead adder (QCLA) to convert a redundant number into a non-redundant number. The chip of a CMOS 4/spl times/4-digit quaternary multiplier is fabricated in cooperation with the VLSI Design and Education Center of Tokyo University, Japan. The chip and core sizes of the multiplier are 2.3/spl times/2.3 mm/sup 2/ and 1.5/spl times/1.6 mm/sup 2/, respectively with 1.5 /spl mu/m technology. The layout design of a 16/spl times/16-digit quaternary multiplier with 0.8 /spl mu/m technology is also discussed for the practical use.

Pipelined Carry Lookahead Adder Design in Quantum-dot Cellular Automata

Abstract: Quantum-dot cellular automata (QCA) is a novel nanotechnology for electronic circuits. The QCA cell is a funda- mental building block. QCA circuits are different from transistor circuits mainly because the basic computational gate is a majority gate and interconnections consume time and area. It's easy to design a pipelined circuit and coplanar wire crossings for a two dimensional structure, but complex designs consume more time due to the wire. The estimation of timing is difficult until the layout is finished. This paper proposes a pipelined carry lookahead adder design in QCA. Using the QCADesigner, 4, 16, and 64 bit carry lookahead adders are designed and simulated. Those designs are compared with ripple carry adders according to the complexity, area, and timing. The final layouts show modular designs and small delays for the carry lookahead adder.

Variable threshold voltage keeper for contention reduction in dynamic circuits

Abstract: A variable threshold voltage keeper circuit technique is proposed for simultaneous power reduction and speed enhancement of domino logic circuits. The threshold voltage of the keeper transistor is dynamically modified during circuit operation to reduce the contention current without sacrificing noise immunity. A four-bit multiple-output domino carry generator for a carry lookahead adder is designed with the proposed circuit technique. It is shown that the variable threshold voltage keeper circuit technique enhances the circuit evaluation speed by up to 60% while reducing power dissipation by 37% as compared to a standard domino logic circuit. It is also shown that the proposed domino logic circuit technique offers 20% higher noise immunity as compared to a standard domino circuit with the same evaluation delay characteristics.