Carry-lookahead adder

About: Carry-lookahead adder is a research topic. Over the lifetime, 243 publications have been published within this topic receiving 3794 citations.

A 1.2 V 500 MHz 32-bit carry-lookahead adder

Abstract: In this paper a 1.2 V 32-bit carry lookahead adder is proposed for high speed, low voltage applications. The proposed new 32-bit adder uses Non-full Voltage Swing True-Single-Phase-Clocking Logic (NSTSPC) to implement the proposed carry lookahead adder. Because the internal node of NSTSPC was non-full swing, its operation speed would be higher than the conventional TSPC. Moreover, the supply voltage for the new adder is 1.2 V, thus the power dissipation would also be reduced. The 32-bit CLA adder using 0.35 /spl mu/m 1P4M CMOS technology with 1.2 V power supply could be operated at a 500 MHz clock frequency.

Design and implementation of a high performance multiplier using HDL

Abstract: This paper presents an area efficient implementation of a high performance parallel multiplier. Radix-4 Booth multiplier with 3:2 compressors and Radix-8 Booth multiplier with 4:2 compressors are presented here. The design is structured for m × n multiplication where m and n can reach up to 126 bits. Carry Lookahead Adder is used as the final adder to enhance the speed of operation. Finally the performance improvement of the proposed multipliers is validated by implementing a higher order FIR filter. The design entry is done in VHDL and simulated using ModelSim SE 6.4 design suite from Mentor Graphics. It is then synthesized and implemented using Xilinx ISE 9.2i targeted towards Spartan 3 FPGA.

Tailoring Tests for Functional Binning of Integrated Circuits

Abstract: In recent years, a number of high level applications have been reported to be tolerant to errors resulting from a sizable fraction of all single stuck-at faults in hardware. Production testing of devices targeted towards such applications calls for a test vector set that is tailored to maximize the coverage of faults that lead to functionally malignant errors while minimizing the coverage of faults that produce functionally benign errors. Given a partitioning of the fault set as benign and malignant, and a complete test vector set that covers all faults, in this paper, we formulate an integer linear programming (ILP) problem to find an optimal test vector set that ensures 100% coverage of malignant faults and minimizes coverage of benign faults.We also propose a test strategy based on selectively masking appropriate outputs of the circuit to partition the circuits at production test into three bins - malignant, benign, and fault-free. As a case study, we demonstrate the proposed ILP based test optimization and functional binning on three adder circuits: 16-bit ripple carry adder, 16-bit carry lookahead adder, and 16-bit carry select adder. We find that the proposed ILP based optimization gives a reduction of about 90% in fault coverage of benign faults while ensuring 100% coverage of malignant faults. This typically translates to an (early manufacturing) yield improvement of over 20% over what would have been the yield if both malignant and benign faults are targeted without distinction by the test vectorset.

Phase-mode pipelined parallel multiplier

Abstract: We propose a pipelined parallel multiplier in phase-mode logic. The multiplier can be composed of combinations of gates which are the basic devices of the phase-mode logic. Experimental operations of the ICF gate and the Adder cell for the multiplier are reported. The proposed multiplier has a Wallace-tree structure comprising trees of carry save adders for the addition of partial products. This structure has a regular layout, hence it is suitable for a pipeline scheme. In the final stage of multiplication, a fast carry lookahead adder is used for generating a multiplication result. Using a Verilog-HDL simulation, we show that the parallel multiplier with 2.5 kA/cm/sup 2/ Nb/AlO/sub x//Nb junctions can operate over 10 GHz.

Carry lookahead adder

Abstract: A high-performance carry lookahead adder (CLA) which can reduce the delay time of the whole adder by constructing a carry generator used therein with NMOS logics, thereby effecting a high-speed operation of the adder along with a lower power-consumption. The carry generator receives an exclusive-OR value P(i, i=1,2,3,4) and a logic product value G(i) of two data, and an initial carry value C(1), and performs a function of G(4)+P(4)·G(3)+P(4)·P(3)·G(2)+P(4)·P(3)·P(2)·G(1)+P(4)·P(3)·P(2)·P(1)·C(1) to output a final carry value C(5). The carry generator includes a first NMOS transistor for executing an operation of P(4)·G(3), second and third NMOS transistors for executing an operation of P(4)·P(3)·G(2), fourth to sixth NMOS transistors for executing an operation of P(4)·P(3)·P(2)·G(1), seventh to eleventh NMOS transistors for executing an operation of P(4)·P(3)·P(2)·P(1)·C(1), and twelfth to fourteenth NMOS transistors for outputting the final carry signal C(5) by an OR operation of the respective logic product terms.