Carry-lookahead adder

About: Carry-lookahead adder is a research topic. Over the lifetime, 243 publications have been published within this topic receiving 3794 citations.

Adder circuits and magnitude comparator

Abstract: An evaluation tree circuit is disclosed that produces a generate, a propagate, and a zero output for use in carry lookahead adders. Another evaluation tree circuit is disclosed that merges the generate, propagate, and zero signals from several adjacent bits or groups of bits. These evaluation trees may be used in self-resetting CMOS or CVSL circuits. They can be used to reduce the number of levels of logic in a carry lookahead adder. They can also be used to form a magnitude comparator, which is also disclosed.

Designing low-power energy recovery adders based on pass transistor logic

Abstract: The novel design of various adiabatic adders based on pass transistor logic is introduced. Also, a new 1-bit full adder basic cell with a small number of transistors is designed. The architectural design of each adiabatic adder and new formulas for their corresponding delay, are presented. The performance of various adiabatic adders, in this work, against the performance of theirs CMOS counterparts, is discussed. All adders (i.e. conventional CMOS and adiabatic) were simulated by the PowerMill tool for power dissipation, latency and energy efficiency. In addition, a first estimation of area was done by the transistor count. Also all adders were simulated at 3.3 V and 5 V, for a broad range of frequencies. Experimental results indicate that the adiabatic adders outperform the corresponding conventional adders in terms of power consumption, and exhibit a lower hardware complexity.

Enhanced fast multiplier.

Abstract: A Wallace-type binary tree multiplier (Fig 3) in which the partial products (Fig 2) of a multiplicand and a multiplier are produced and then successively reduced using a plurality of adder levels (L1, L2, L3, L4, Fig 3) comprised of full and half adders (FA, HA, Fig 3) This reduction continues until a final set of inputs (Level L4, Fig 3) is produced wherein no more than two inputs remain to be added in any column This final set is then added using a serial adder (20) and a carry lookahead adder (21) to produce the desired product (po-p15) The additions at leach level are performed in accordance with prescribed rules to provide for fastest overall operating speed and minimum required chip area In addition, the lengths of the serial adder (20) and carry lookahead adder (21) are chosen to further enhance speed while reducing required chip area A still further enhancement in multiplier operating speed is achieved by providing connections to adders (Fig 3) so as to take advantage of the different times of arrival of the inputs to each level (levels L1, L2, L3, L4 in Fig 3) along with different adder input-to-output delays

Optimizing adders for WSI

Abstract: The authors report on the speed and dynamic power dissipation of CMOS implementations of six different adders. The adders are constructed with inverters and two-to-four-input AND and OR gates. A figure of merit is presented that can be used to compare the adders based on their delay and relative dynamic power consumption. This figure of merit provides a common ground for ranking the adders in terms of their utility for WSI (wafer scale integration) applications. Extensive simulation was used to evaluate the switching characteristics, and the results are used to rank the adders in terms of speed, size, and the number of logic transitions (a measure of the dynamic power consumption for static CMOS circuits). According to the figure of merit, the carry lookahead adder is the best design for word sizes between 16 and 64 bits, inclusive. >

An improved 32-bit carry-lookahead adder with Conditional Carry-Selection

Abstract: An improved 32-bit carry-lookahead adder (CLA) with Conditional Carry-Selection (CSS) is proposed in this paper. The new adder is compared with Serial Adder and pure Carry-Lookahead Adder. The three adders is simulated in FPGA circuits, the results show that the propagation time of the carry of the new 32-bit adder is reduced 26% compared with Serial Adder and 3.17% with pure Carry-Lookahead Adder.