Carry-lookahead adder

About: Carry-lookahead adder is a research topic. Over the lifetime, 243 publications have been published within this topic receiving 3794 citations.

A new architecture for fast modular multiplication

Abstract: An algorithm for computing AB mod N is developed, where N can be any positive integer Since a carry-save adder can be used to implement the algorithm, a VLSI (very-large-scale integration) multiplier with area O(n) for multiplying n-bit integers is very fast It is shown that n-bit AB mod N operation with 2/sup n-1/ >

Asynchronous early output section-carry based carry lookahead adder with alias carry logic

Abstract: A new asynchronous early output section-carry based carry lookahead adder (SCBCLA) with alias carry output logic is presented in this paper. To evaluate the proposed SCBCLA with alias carry logic and to make a comparison with other CLAs, a 32-bit addition operation is considered. Compared to the weak-indication SCBCLA with alias logic, the proposed early output SCBCLA with alias logic reports a 13% reduction in area without any increases in latency and power dissipation. On the other hand, in comparison with the early output recursive CLA (RCLA), the proposed early output SCBCLA with alias logic reports a 16% reduction in latency while occupying almost the same area and dissipating almost the same average power. All the asynchronous CLAs are quasi-delay-insensitive designs which incorporate the delay-insensitive dual-rail data encoding and adhere to the 4-phase return-to-zero handshaking. The adders were realized and the simulations were performed based on a 32/28nm CMOS process.

A low-power 2.1 GHz 32-bit carry lookahead adder using Dual Path All-N-Logic

Abstract: A high-speed, low-power 32-bit carry lookahead adder is presented. We have developed Dual Path All-N-Logic (DPANL) and applied to 32-bit adder design for higher performance. The speed enhancement is mainly due to reduced capacitance at each evaluation node of dynamic circuits. This adder can operate at frequencies up to 2.1GHz for 0.35um 1P4M CMOS technology and is 31.3% and 27.3% faster than the adders using All-N-Transistor (ANT) and All-N-Logic (ANL), respectively. It also consumes 29.2% and 15.4% less power than the ANT adder and ANL adder, respectively.

Asynchronous Early Output Section-Carry Based Carry Lookahead Adder with Alias Carry Logic

Abstract: A new asynchronous early output section-carry based carry lookahead adder (SCBCLA) with alias carry output logic is presented in this paper. To evaluate the proposed SCBCLA with alias carry logic and to make a comparison with other CLAs, a 32-bit addition operation is considered. Compared to the weak-indication SCBCLA with alias logic, the proposed early output SCBCLA with alias logic reports a 13% reduction in area without any increases in latency and power dissipation. On the other hand, in comparison with the early output recursive CLA (RCLA), the proposed early output SCBCLA with alias logic reports a 16% reduction in latency while occupying almost the same area and dissipating almost the same average power. All the asynchronous CLAs are quasi-delay-insensitive designs which incorporate the delay-insensitive dual-rail data encoding and adhere to the 4-phase return-to-zero handshaking. The adders were realized and the simulations were performed based on a 32/28nm CMOS process.