Carry-lookahead adder

About: Carry-lookahead adder is a research topic. Over the lifetime, 243 publications have been published within this topic receiving 3794 citations.

A low-power 1.85 GHz 32-bit carry lookahead adder using Dual Path All-N-Logic

Abstract: We have developed Dual Path All-N-logic (DPANL) and applied to 32-bit adder design for higher performance. The speed enhancement is mainly due to reduced capacitance at each evaluation node of dynamic circuits. Post-layout simulation results show that this adder can operate at frequencies up to 1.85 GHz for 0.35 /spl mu/m 1P4M CMOS technology and is 32.4% faster than the adder using all-N-transistor (ANT). It also consumes 29.2% less power than the ANT adder. A 0.35 /spl mu/m CMOS chip has been fabricated and tested to verify the functionality and performance of the DPANL adder on silicon.

Fully pipelined parallel multiplier with a fast clock cycle

Abstract: A fully pipelined parallel multiplier with a fast clock cycle. The pipelined parallel multiplier contains three units: a bit-product matrix unit, a reduction unit, and an addition unit. The bit-product matrix is configured to receive two binary numbers, a multiplier and a multiplicand. A bit-product matrix is formed based on these two numbers. The bit-product matrix unit forms a first pipeline stage. The bit-product matrix is latched to the reduction unit using d-type latch circuits. The reduction unit includes a plurality of reduction stages, with each reduction stage acting as a pipeline stage. The reduction unit reduces the matrix down to a two-row matrix. Intermediate results are latched from one stage to the next using d-type latch circuits. The reduction unit also contains a plurality of half-adder and full-adder circuits. The final two-row matrix formed by the reduction unit is then latched to an addition unit. The addition unit includes one or more stages of addition, with each stage also acting as a pipeline stage. Carry lookahead adder (CLA) circuits are cascaded to perform the addition, with one CLA per addition stage. Results from each addition stage are latched to the next stage using d-type latch circuits. The output from the final stage is the final product of the multiplication.

A 10 ns 54atimes;54-bit parallel structured full array multiplier with 0.5 amu;m CMOS technology

Abstract: A 54-bt54-b multiplier fabricated in double metal 0.5-mm CMOS technology is described. A 10-ns multiplication time has been achieved by employing a 4-2 compressor, a carry select adder, and a carry lookahead adder. The 54-bt54-b full array is adopted to complete the multiplication within one latency. This multiplier is intended for double-precision floating-point data processing based on IEEE standards up to a clock range of 100 MHz. The multiplier has integrated 81600 transistors in an active area of 3.62 mmt3.45 mm

Optimization and Speed Improvement Analysis of Carry-Lookahead Adder Structure

Abstract: The delay characteristics of carrylookahead (CLA) adders are examined with respect to a delay model that accounts for fan-in and fanout dependencies. Though CLA structures are considered among the fastest topologies for performing addition, they have also been characterized as providing marginal speed improvement for the amount of hardware invested. This analysis shows that this inefficiency can be explained by the suboptimal nature of common CLA implementations. Simulation results show that the CLA structures in wide use can be improved by varying the block sizes and the number of levels within each adder. Examples of optimal CLA structures are given and heuristic methods for finding these structures are presented.

Improved non-restoring division algorithm with dual path calculation

Abstract: This paper focuses on improving the performance of non-restoring division by reducing the delay. To improve its performance, two new approaches are proposed here. For the first proposed approach, a novel method to find a quotient bit for every iteration, which hides the total delay of the multiplexer with dual path calculation is presented. The second new method uses a modified Most Significant Carry (MSC) generator, which determines the sign of each remainder faster than a carry lookahead adder. This reduces the total delay.