Carry-lookahead adder

About: Carry-lookahead adder is a research topic. Over the lifetime, 243 publications have been published within this topic receiving 3794 citations.

Performance analysis of 64-bit Carry Lookahead Adders using conventional and hierarchical structure styles

Abstract: This paper introduces performance analysis of 64-bit Carry Lookahead Adders using conventional and hierarchical structure styles. We evaluate conventional carry lookahead adder (CLA) and hierarchical carry lookahead adder (HCLA) using different parameters. Our design is targeted into FPGA Virtex 7 family. Area, delay, and area-delay product of all design choices are reported. In the experimental results, we reduced CLA delay and area using radix-2 which performed better than traditionally used radix-4 CLA. In addition, we showed that CLA using conventional structure has better performance than the hierarchical structure.

All-optical prefix tree adder with the help of terahertz optical asymmetric demultiplexer

Abstract: We propose and describe an all-optical prefix tree adder with the help of a terahertz optical asymmetric demultiplexer (TOAD) using a set of optical switches. The prefix tree adder is useful in compound adder implementation. It is preferred over the ripple carry adder and the carry lookahead adder. We also describe the principle and possibilities of the all-optical prefix tree adder. The theoretical model is presented and verified through numerical simulation. The new method promises higher processing speed and accuracy. The model can be extended for studying more complex all-optical circuits of enhanced functionality in which the prefix tree adder is the basic building block.

64-bit pipeline carry lookahead adder using ALL-N-transistor TSPC logics

Abstract: This paper proposes two improved circuit techniques of True Single-Phase Clocking (TSPC) logic, which called Nonfull Swing TSPC (NSTSPC) and All-N-TSPC (ANTSPC). The voltage of internal node of the NSTSPC is not full swing; it saves partial dynamic power dissipation. And the ANTSPC uses NMOS transistors to replace PMOS transistors, the output loading of Φ-section is therefore reduced and a higher layout density is obtained. Through postlayout simulation comparisons between number of stacked MOS transistors and delay time, and supply voltage vs maximum frequency, the proposed NSTSPC and ANTSPC circuits show better operation speed and power performance than the conventional TSPC circuit. Finally, the new TSPC circuits are applied to a 64-bit hierarchical pipeline Carry Lookahead Adder (CLA), which based on TSMC 0.35 μm CMOS process technology. By using the techniques of NSTSPC and ANTSPC alternately, the 64-bit CLA is successfully implemented as a pipelined structure. The results of post-layout simulation show that the 64-bit CLA can be operated on 1.25 GHz clock frequency and its power/maximal frequency ratio is 151.4 μW/MHz.

T-count and Qubit Optimized Quantum Circuit Designs of Carry Lookahead Adder.

Abstract: Quantum circuits of arithmetic operations such as addition are needed to implement quantum algorithms in hardware. Quantum circuits based on Clifford+T gates are used as they can be made tolerant to noise. The tradeoff of gaining fault tolerance from using Clifford+T gates and error correcting codes is the high implementation overhead of the T gate. As a result, the T-count performance measure has become important in quantum circuit design. Due to noise, the risk for errors in a quantum circuit computation increases as the number of gate layers (or depth) in the circuit increases. As a result, low depth circuits such as quantum carry lookahead adders (QCLA)s have caught the attention of researchers. This work presents two QCLA designs each optimized with emphasis on T-count or qubit cost respectively. In-place and out-of-place versions of each design are shown. The proposed QCLAs are compared against the existing works in terms of T-count. The proposed QCLAs for out-of-place addition achieve average T gate savings of $54.34 \%$ and $37.21 \%$, respectively. The proposed QCLAs for in-place addition achieve average T gate savings of $72.11 \%$ and $35.87 \%$

Efficient VLSI implementation of statistical carry lookahead adder

Abstract: A new efficient VLSI implementation of a statistical carry lookahead adder is presented. The new circuit does not require precharged input signals, and it can be used in practical asynchronous system design and in mixed logic design without any auxiliary circuitry. The circuit is realised in domino logic, and DCVSL gates are used for the critical path.