Carry-lookahead adder

About: Carry-lookahead adder is a research topic. Over the lifetime, 243 publications have been published within this topic receiving 3794 citations.

A Structured Approach for Optimizing 4-Bit Carry-Lookahead Adder

Abstract: This paper presents a comparative research of low-power and high-speed 4-bit full adder circuits. The represen- tative adders used are a ripple carry adder (RCA) and a carry-lookahead adder (CLA). We also design a proposed carry- lookahead adder (PCLA) using a new method that uses NAND gate for modification which helps in reducing the power- delay product (PDP) for high performance applications. To yield more realistic rise and fall times in the simulations, lay- outs have been made in a 0.13 � m process for the RCA circuit, CLA circuit and PCLA circuit. The layouts designed were simulated by HSPICE based on 130 nm CMOS technology at 1.2 V supply voltages. Four sets of frequencies were oper- ated: 10 MHz, 50 MHz, 100 MHz and 500 MHz with 50% duty cycle in different technology corner models. A compre- hensive comparison and analysis were also carried out to test the performance of the adders. The three adders also yield different performances in terms of power consumption, PDP, and area. The simulation results of this research are ex- pected to help designers to select the appropriate 4-bit adder cell that meets their specific applications.

Efficient Multiply-by-3 and Divide-by-3 Algorithms and Their Fast Hardware Implementation

Abstract: SUMMARY This study presents efficient algorithms for performing multiply-by-3 (3N) and divide-by-3 (N/3) operations with the additions and subtractions, respectively. No multiplications and divisions are needed. Full adder (FA) and full subtractor (FS) can be implemented to realize the N3 and N/3 operations, respectively. For fast hardware implementation, this paper introduces two basic cells UCA and UCS for 3N and N/3 operations, respectively. For 3N operation, the UCA-based ripple carry adder (RCA) and carry lookahead adder (CLA) designs are proposed and their speed performances are estimated based on the delay data of standard cell library in TSMC 0.18µm CMOS process. Results show that the 16-bit UCA-based RCA is about 3 times faster than the conventional FA-based RCA and even 25% faster than the FA-based CLA. The proposed 16-bit and 64-bit UCA-based CLAs are 62% and 36% faster than the conventional FA-based CLAs, respectively. For N/3 operations, ripple borrow subtractor (RBS) is also presented. The 16-bit UCS-based RBS is about 15.5% faster than the 16-bit FS-based RBS.

A pipelined clock-delayed domino carry-lookahead adder

Abstract: Clock-delayed (CD) domino is a dynamic logic family developed to provide both inverting and non-inverting logic on single-rail gates. It is self-timed and can be easily pipelined for superior speed performance which makes it an attractive option in high-speed logic implementation. This paper presents the design of two different high-speed pipeline configurations of a 32-bit carry look-ahead adder using CD domino gates utilizing efficient clocking methodology to reduce the overall critical path delay.