Carry-lookahead adder

About: Carry-lookahead adder is a research topic. Over the lifetime, 243 publications have been published within this topic receiving 3794 citations.

Investigation of properties of 36-bit adders for creation of DSP blocks on FPGA

Abstract: In this paper 36-bit ripple-carry, carry-skip, carry-select and carry-lookahead adders intended for using in field programmable gate arrays are investigated. These schemes implemented in CMOS 0.18 µm technology are compared for their performance. The size of adders is estimated.

A Novel Nanometric Parity-Preserving Reversible Carry-Lookahead Adder

Abstract: During recent years, reversible logic received important attention in cryptography, optical processing, quantum computing, and nanotechnology. Among the reversible computation units, the adder unit is considered the most fundamental computation unit to build a quantum computing system. Due to its low latency, the reversible carry-lookahead adder is mostly used and considered. Parity preserving is also one of the oldest methods for error recognition in digital systems. In this article, we offer new proposals for the nanometric parity-preserving reversible 2-bit carry-lookahead adder. Compared with previous designs, we will demonstrate that our designs would be optimal in the number of garbage outputs, constant inputs, and quantum costs. In order to design circuits at a higher level, we also offer new proposals for the nanometric parity-preserving reversible 4-bit carry-lookahead adder. Since previous proposals that were presented as 4-bit did not have the reversible parity-preserving property, we p...

Speed and Energy Optimised Quasi-Delay-Insensitive Block Carry Lookahead Adder

Abstract: We present a new asynchronous quasi-delay-insensitive (QDI) block carry lookahead adder with redundancy carry (BCLARC) realized using delay-insensitive dual-rail data encoding and 4-phase return-to-zero (RTZ) and 4-phase return-to-one (RTO) handshaking. The proposed QDI BCLARC is found to be faster and energy-efficient than the existing asynchronous adders which are QDI and non-QDI (i.e., relative-timed). Compared to existing asynchronous adders corresponding to various architectures such as ripple carry adder (RCA), conventional carry lookahead adder (CCLA), carry select adder (CSLA), BCLARC, and hybrid BCLARC-RCA, the proposed BCLARC is found to be faster and more energy-optimised. The cycle time (CT), which is the sum of forward and reverse latencies, governs the speed; and the product of average power dissipation and cycle time viz. the power-cycle time product (PCTP) defines the low power/energy efficiency. For a 32-bit addition, the proposed QDI BCLARC achieves the following average reductions in design metrics over its counterparts when considering RTZ and RTO handshaking: i) 20.5% and 19.6% reductions in CT and PCTP respectively compared to an optimum QDI early output RCA, ii) 16.5% and 15.8% reductions in CT and PCTP respectively compared to an optimum relative-timed RCA, iii) 32.9% and 35.9% reductions in CT and PCTP respectively compared to an optimum uniform input-partitioned QDI early output CSLA, iv) 47.5% and 47.2% reductions in CT and PCTP respectively compared to an optimum QDI early output CCLA, v) 14.2% and 27.3% reductions in CT and PCTP respectively compared to an optimum QDI early output BCLARC, and vi) 12.2% and 11.6% reductions in CT and PCTP respectively compared to an optimum QDI early output hybrid BCLARC-RCA. The adders were implemented using a 32/28nm CMOS technology.

Circuit suitable for use in a carry lookahead adder

Abstract: An adder circuit for determining the sum of two operands including a set of PGK circuits, at least one tier of group circuits, and a carry generation circuit. The PGK circuits generate propagate, generate, and kill bits corresponding to at least a portion of the first and second operands. The group circuit receives propagate, generate, and kill bits from a plurality of the PGK circuits and produces a set of group propagate, generate, and kill values. The carry generation circuit receives a carry-in bit and the outputs of at least one of the group circuits and generates a carry-out bit representing the carry-out of the corresponding group. The PGK circuits, group circuits, and carry circuits may use CMOS transmission gates in lieu of conventional complementary pass-gate logic (CPL).

High-precision multi-channel time-to-digital converter

Abstract: The invention discloses a high-precision multi-channel time-to-digital converter (TDC) The time-to-digital converter adopts a two-stage structure; the first-stage structure adopts a pulse counting type time-to-digital converter based on a carry lookahead adder, and is used for achieving a high working frequency and a wide dynamic range; and the second-stage structure adopts a multi-channel time-to-digital converter based on a voltage-controlled differential time delay unit and a true single phase clocked trigger, and the second-stage structure is used for improving the measurement precision and reducing the measurement error According to the product, the principle of two-stage measurement is utilized, so that the dynamic range and the resolution ratio are taken into consideration A voltage-controlled differential phase inverter and the true single phase clocked (TSPC) trigger are used in the second-stage TDC, so that good linearity and low error rate of a system are ensured; and meanwhile, an integral framework adopts a three-channel structure, so that the length of a single time delay chain is reduced by 2/3, the uncertainty is reduced by 43%, and the performance of the systemis effectively improved