Carry-lookahead adder

About: Carry-lookahead adder is a research topic. Over the lifetime, 243 publications have been published within this topic receiving 3794 citations.

P hase-Mode P ipelined Parallel Multiplier

Abstract: We propose a pipelined parallel multiplier in phase-mode logic. The multiplier can be composed of combinations of gates which are the basic devices ofthe phase- mode logic. Experimental operations of the ICF gate and the Adder cell for the multiplier are reported. The proposed multiplier has a Wallace-tree structure comprising trees of carry save adders for the addition of partial products. This structure has a regular layout, hence it is suitable for a pipeline scheme. In the final stage of multiplication, a fast carry lookahead adder is used for generating a multiplication result. Using a Verilog-HDL simulation, we show that the parallel multiplier with 2.5kA/cm2 Nb/AlOx/Nb junctions can operate over 10 GHz.

Threshold logic type carry lookahead adder comprising SET/MOS (Single Electron Transistor/Metal Oxide Semiconductor) hybrid circuit

Abstract: The utility model relates to a threshold logic type carry lookahead adder comprising a SET/MOS (Single Electron Transistor/Metal Oxide Semiconductor) hybrid circuit, which comprises a carry lookahead logic module, a first additive operation module and a second additive operation module; by utilizing the Coulomb blockade oscillation effect and multi-grid input characteristic of a single electron transistor and MOS transistor structure, the threshold logic-based carry lookahead adder comes into being. Because of the powerful logic function of threshold logic, the circuit only consists of ten threshold logic gates, and only thirty elements are used by the entire circuit. Compared with a conventional pure CMOS (Complementary Metal Oxide Semiconductor) carry lookahead adder, the circuit structure of the threshold logic type carry lookahead adder is greatly simplified, the number of transistors is remarkably reduced, and thereby the power consumption of the circuit is further reduced. The threshold logic type carry lookahead adder is expected to be applied in the fields of microprocessors, digital signal processors and the like, and can be in favor of further reducing the power consumption of circuits, save the chip area and increase the integration degree of circuits.

Design of 32Bit Carry-lookahead Adder using Constant Delay Logic

Abstract: This paper presents an enhanced 32-bit carry look- ahead(CLA) adder implementing using the constant delay (CD) logic, targeting at full-custom high-speed applications. The CD characteristic of this logic style regardless of the logic type makes it suitable in implementing complicated logic expressions such as addition. CD logic exhibits a unique characteristic where the output is pre-evaluated before the inputs from the preceding stage is ready. This feature offers performance advantage over static and dynamic domino logic styles in a single-cycle multistage circuit block. Several design considerations including timing window width adjustment and clock distribution are discussed. Using 65-nm general-purpose CMOS technology, the proposed logic demonstrates an average speed up of 94% and 56% over static and dynamic domino logic, respectively, in five different logic gates. Simulation results of 8-bit ripple carry adders show that CD logic is 39% and 23% faster than the static and dynamic-based adders, respectively. CD logic also demonstrates 39% speedup and 64%(22%) energy-delay product (EDP) reduction from static logic at 100% (10%) data activity in 32-bit carry look ahead adders. For 8-bit Wallace tree multiplier, CD logic achieves a similar speedup with at least 50% EDP reduction across all data activities.

15GHz low-voltage-swing carry-lookahead adder

Abstract: We describe a high speed adder that employs a carry-lookahead structure and uses low-voltage-swing pass-transistor-based Manchester carry chain. This structure is implemented in 65nm technology and accommodates 15GHz clock frequency at the slowest corner which is 20% higher than the highest speed in the previously studied high-speed structures.

Latency Optimized Asynchronous Early Output Ripple Carry Adder based on Delay-Insensitive Dual-Rail Data Encoding

Abstract: Asynchronous circuits employing delay-insensitive codes for data representation i.e. encoding and following a 4-phase return-to-zero protocol for handshaking are generally robust. Depending upon whether a single delay-insensitive code or multiple delay-insensitive code(s) are used for data encoding, the encoding scheme is called homogeneous or heterogeneous delay-insensitive data encoding. This article proposes a new latency optimized early output asynchronous ripple carry adder (RCA) that utilizes single-bit asynchronous full adders (SAFAs) and dual-bit asynchronous full adders (DAFAs) which incorporate redundant logic and are based on the delay-insensitive dual-rail code i.e. homogeneous data encoding, and follow a 4-phase return-to-zero handshaking. Amongst various RCA, carry lookahead adder (CLA), and carry select adder (CSLA) designs, which are based on homogeneous or heterogeneous delay-insensitive data encodings which correspond to the weak-indication or the early output timing model, the proposed early output asynchronous RCA that incorporates SAFAs and DAFAs with redundant logic is found to result in reduced latency for a dual-operand addition operation. In particular, for a 32-bit asynchronous RCA, utilizing 15 stages of DAFAs and 2 stages of SAFAs leads to reduced latency. The theoretical worst-case latencies of the different asynchronous adders were calculated by taking into account the typical gate delays of a 32/28nm CMOS digital cell library, and a comparison is made with their practical worst-case latencies estimated. The theoretical and practical worst-case latencies show a close correlation....