Topic
Carry-lookahead adder
About: Carry-lookahead adder is a research topic. Over the lifetime, 243 publications have been published within this topic receiving 3794 citations.
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01 Dec 2019
TL;DR: An energy efficient and novel Charge Sharing Complementary Pass Transistor Adiabatic Logic operated by four phase power clock is proposed, which realizes low switching noise and incurs low leakage power.
Abstract: An energy efficient and novel Charge Sharing Complementary Pass Transistor Adiabatic Logic (CSCPAL) operated by four phase power clock is proposed. It realizes low switching noise and incurs low leakage power. FinFETs are ideal devices for low power circuit design due to their enhanced properties of reduced short channel effects and lower leakage current. The circuits are designed using 32nm FinFET models and are simulated using Cadence® Virtuoso design tools. Efficiency of FinFET based CSCPAL is compared with FinFET based 2N2N2P, 2N2P and PFAL designs found in the literature. Energy consumption of CSCPAL Inverter/Buffer, AND and XOR sub modules used in the design of 8-bit Carry Lookahead Adder circuits have been compared with the 2N2P, 2N2N2P and PFAL based circuit counterparts. 8-bit CLA is taken as a benchmark circuit for validation of energy efficiency.
01 Jan 1997
TL;DR: Preliminary simulation results by Mentor Graphics at static gate-level have indicated that IPP adders are faster than Tyagi's 16-bit, 32-bit and 64-bit Select-Prefix Adders(5).
Abstract: A schematic of a new 64-bit adder is pre- sented in this paper. This adder uses the Manchester Carry Chain carry lookahead modules with spans of 4,3, and 2. Only the first level has intermediate outputs. Unlike carry-ripple adders at the output of the Spanning Tree Carry Lookahead Adder(SPT)(l,t) and the Recur- sive Carry-LookaheadCarry-Select Hybrid Adder (RCS)(3), the proposed Irregular Parallel-Prefix WP) adder provided parallel addition at the output thus signif- icantly reducing the number of transistors with a prom- ising compatible speed. This wifl cause a considerabIe improvement in cost-performance. Without a carry-skip circuit, this adder also works well with a carry-in of "1" based on Brent-Kung and Tyagi's lemmas (4$). Because the IPP adder is unidirectional, it is more appropriate for pipeline implementation. Preliminary simulation results by Mentor Graphics at static gate-level have indicated that IPP adders are faster than Tyagi's 16-bit, 32-bit and 64-bit Select-Prefix Adders(5). SPICE simulation at a transistor-level for a 16-bit IPP adder shows a speed of 1.756 ns. It reduces the transistor-count approximately by 21% compared to the RCS adder(3) and by 18% com- pared to the SPT adder( 1,2).
Journal Article•
TL;DR: In this article, the authors present an all-optical implementa-tion of a digital multiplexer using MZI switches, where both non-reversible and reversible verifications of the design are proposed, along with analytical evaluation of the complexity both in terms of delay and resource requirements.
Abstract: With the advancements in semiconductor technology, there has been an increased emphasis in low-power design techniques over the last few decades. Now-a-days, semiconductor optical amplifier (SOA)- based Mach–Zehnder interferometer (MZI) plays a vital role in the field of ultra-fast all-optical signal processing. Reversible computing has been proposed by several researchers as a possible alternative to address the energy dissipation problem. Several implementation alternatives for reversible logic circuits have also been explored in recent years, like adiabatic logic, nuclear magnetic resonance, optical computing, etc. Recently researchers have proposed implementations of various reversible logic circuits in the all-optical computing domain. Most of these works are based on semiconductor optical amplifier (SOA) based Mach-Zehnder interferometer (MZI), which provides desirable features like low power, fast switching and ease of fabrication. In this paper we present an all-optical implementation of a digital multiplexer using MZI switches.we exploring this project with MZI based Carry lookahead Adder(CLA). Both non-reversible and reversible versions of multiplexer design are proposed, along with analytical evaluation of the design complexities both in terms of delay and resource requirements. The final optical netlists obtained have been compared against traditional reversible synthesis approaches, by using an available synthesis tool and then mapping the reversible gates to MZI switch based implementations. Some techniques for optimizing the final optical netlists have also been proposed.
TL;DR: Two general architectures of Carry Select Adder have been introduced for high speed addition that utilize the hybridized structure of Carry Lookahead Adder and Ripple Carry Adder to reduce the critical path delay.
Abstract: In this paper, two general architectures of Carry Select Adder (CSA) have been introduced for high speed addition. These CSA architectures utilize the hybridized structure of Carry Lookahead Adder (CLA) and Ripple Carry Adder (RCA). In these architectures the critical path delay has been reduced by reducing the number of multiplexer stages. The proposed designs are compared with regular CSA based on RCA. The second architecture showed 11.3%, 3.9% improvement in delay and an overhead of 13% in area.
25 Jul 2004
TL;DR: This paper presents a method of identifying a minimal complete set of test vectors for detecting all single stuck-at faults for a pyramidal carry lookahead adder, of any size, together with results.
Abstract: The paper is the result of the authors activities concerning the testing and the design for testability for computer arithmetic systems. By applying the C-testability concept which is presented in, we present a method of identifying a minimal complete set of test vectors for detecting all single stuck-at faults for a pyramidal carry lookahead adder, of any size, together with our results.