Carry-lookahead adder

About: Carry-lookahead adder is a research topic. Over the lifetime, 243 publications have been published within this topic receiving 3794 citations.

Design of high performance double precision hybrid ALU for SoC applications

Abstract: In this paper, we have presented a design of hybrid arithmetic logic unit (ALU) in Double precision format (DPF) according to the IEEE-754 standard. In this we have designed an ALU which consists of the two different architectures. First architecture is semi-floating point unit (Semi-FPU) and the second architecture is floating point unit (FPU). Semi-FPU takes a 32-bit integer input and produces an output in 64-bit DPF. And the floating point unit takes the input in 64-bit DPF and produces the output in 64-bit DPF. FPU also provides rounding and exception handling. Both the architectures can perform addition, subtraction, division, and multiplication. ALU is designed with three different adders which is ripple carry adder, carry lookahead adder, and carry save adder. The parameters such as area, power, and delay is compared for each modules (add, mul, div) of ALU with all three different adders. And according to the power-delay product, the best adder among the above three is chosen for each operation. The sub modules are written in Verilog HDL. For simulation we have used Xilinx ISE software and synthesis is done using cadence Encounter RTL compiler using typical libraries of TSMC 45 nm technology.

Arithmetic operators based on the binary stored-carry-or-borrow representation

Abstract: We introduce implementations of arithmetic operators based on the binary stored-carry-or-borrow (BSCB) representation Several BSCB arithmetic elements, including full-adder, ripple-carry adder, and carry-lookahead adder are presented, followed by detailed design of an array multiplier In the latter design, the conventional initial AND matrix is transformed and expressed with a redundant radix-2 representation Each line of the resulting matrix is processed by an accumulation operator with the BSCB representation Due to a specific property of the multiplication process, this operator is simpler than a standard full-adder cell in terms of gate count, while maintaining the same propagation latency The entire multiplier is implemented with only XOR and AND gates, thus improving its testability and reliability

Super Pipelined Digit Serial Adders for Multimedia and e-Security

Abstract: This paper presents super-pipelined models of conventional adders that use digit serial addition. We pipeline three adders: ripple carry, carry select, and carry lookahead showing the pipelining effect in their speed and area. An improvement to the pipelined carry lookahead adder is proposed showing interesting results.

Pipelined Two-Operand Modular Adders

Abstract: Pipelined two-operand modular adder (TOMA) is one of basic components used in digital signal process- ing (DSP) systems that use the residue number system (RNS). Such modular adders are used in binary/residue and residue/binary converters, residue multipliers and scalers as well as within residue processing channels. The structure of pipelined TOMAs is usually obtained by in- serting an appropriate number of pipeline register layers within a nonpipelined TOMA structure. Hence the area of pipelined TOMAs is determined by the nonpipelined TOMA structure and by the total number of pipeline registers. In this paper we propose a new pipelined TOMA, that has a considerably smaller area and the attainable pipelining frequency comparable with other known pipelined TOMA structures. We perform comparisons of the area and pipe- lining frequency with TOMAs based on ripple carry adder (RCA), Hiasat TOMA and parallel-prefix adder (PPA) using the data from the very large scale of integration (VLSI) standard cell library. n m m m X X X with i m i x Z  . This mapping is the bijection and for X, Y  ZM and for i m i i y x Z  , , we have i m i i i y x z   ,where  denotes addition, subtraction or

ALU circuit in FPGA

Abstract: The invention discloses an ALU circuit in an FPGA and relates to the field of integrated circuit design. The ALU circuit comprises M addition units and a carry lookahead adder, wherein M is an integergreater than or equal to 8; each addition unit comprises a three-input full adder, a first selector, a second selector and a third selector, and output of the second selector and output of the thirdselector of each addition unit are used as output of the corresponding addition unit; each three-input full adder is provided with three input ends and two output ends, namely a sum value data outputend and a carry data output end; a sum value output end of the carry lookahead adder is connected with a first input end of a fourth selector and also connected with a second input end of the fourth selector through an inverter, and an output end of the fourth selector serves as a third output end of the ALU circuit; and the carry lookahead adder is also provided with a first output end used for outputting first carry data and a second output end used for outputting second carry data. Through the ALU circuit, a high-efficiency small-area DSP module is realized.