Topic
Carry-lookahead adder
About: Carry-lookahead adder is a research topic. Over the lifetime, 243 publications have been published within this topic receiving 3794 citations.
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TL;DR: The experimental results of the basic SD arithmetic integrated circuits by means of the bidirectional current-mode circuits and their evaluation show that the addition time of the SD adder is 14 times faster than that of the conventional ripple-carry adder and is three times faster of the block carry lookahead adder.
Abstract: For highly parallel operation, use of a radix-4 signed-digit (SD) number system is attractive. Since the SD number system uses more than three values in each digit, multivalued coding is suitable for the implementation of the high-speed compact arithmetic integrated circuits. We have already proposed the basic idea of multivalued bidirectional current-mode circuits which are essentially suitable for the SD arithmetic implementation. This paper describes the experimental results of the basic SD arithmetic integrated circuits by means of the bidirectional current-mode circuits and their evaluation. A parallel SD adder is implemented with 2-μm CMOS technology and the addition time is estimated to be about 10 ns. The addition time of the SD adder is 14 times faster than that of the conventional ripple-carry adder and is three times faster than that of the block carry lookahead adder.
03 May 2018
TL;DR: A comparative research of Carry Lookahead Adder (CLA) carry chains of various design implementations, in terms of propagation delay and transistor count is presented, establishing, how the physical implementation of circuits relate to their performance.
Abstract: This paper presents a comparative research of Carry Lookahead Adder (CLA) carry chains of various design implementations, in terms of propagation delay and transistor count. Two different design implementations of CLA carry generation circuit are discussed and compared based on their speed and transistor count. The representative designs compared are Complementary Metal Oxide Semiconductor (CMOS) Conventional CLA (CCLA) carry generation structure and proposed structure of CLA carry generation, named VpAn. To yield optimized delay for the proposed VpAn Design, transistor resizing has been done. A comprehensive comparison and analysis of performance of four, eight and sixteen bit carry chains are carried out. All the schematics of the CLA carry chains are designed using 0.25um process. The simulations of the schematics of CMOS conventional CLA generation circuits and the proposed CLA carry generation designs are performed using LTspice based on 250nm CMOS technology and 2.5V supply voltage to yield realistic rise and fall times. The speed of each circuit is evaluated and our proposed model reduces the propagation delay by 75% compared to the results of CCLA before sizing. This paper establishes, how the physical implementation of circuits relate to their performance.
01 Aug 2018
TL;DR: A new asynchronous early output, relative-timed block carry lookahead adder (BCLA) incorporating redundant carries is proposed, which achieves a greater reduction in cycle time and area over the best of existing hybrid CLARCA variants without power penalty.
Abstract: A new asynchronous early output, relative-timed block carry lookahead adder (BCLA) incorporating redundant carries is proposed. Compared to the best of existing semi-custom asynchronous carry lookahead adders (CLAs) employing delay-insensitive data encoding and following a 4-phase handshaking, the proposed BCLA with redundant carries achieves 14.9% reduction in cycle time and 12.3% reduction in area with no power penalty. A hybrid variant involving a ripple carry adder (RCA) in the least significant stages i.e. BCLA-RCA is also considered that achieves 15.2% reduction in cycle time and 11.2% reduction in area over the best of existing hybrid CLARCA variants without power penalty.