Carry-lookahead adder

About: Carry-lookahead adder is a research topic. Over the lifetime, 243 publications have been published within this topic receiving 3794 citations.

A shared-well dual-supply-voltage 64-bit ALU

Abstract: A shared n-well layout technique is developed for the design of dual-supply-voltage logic blocks. It is demonstrated on a design of a 64-bit arithmetic logic unit (ALU) module in domino logic. The second supply voltage is used to lower the power of noncritical paths in the sparse, radix-4 64-bit carry-lookahead adder and in the loopback bus. A 3 mm/sup 2/ test chip in 0.18-/spl mu/m 1.8-V five-metal with local interconnect CMOS technology that contains six ALUs and test circuitry operates at 1.16 GHz at the nominal supply. For target delay increase of 2.8% energy savings are 25.3% using dual supplies, while for 8.3% increase in delay, 33.3% can be saved.

High radix booth multipliers using reduced area adder trees

Abstract: The reduced area multiplier, the Wallace multiplier, and the Dadda (1965) multiplier each offer fast multiplication of signed binary numbers with the use of a large adder tree and a carry lookahead adder. However, their complexity makes them undesirable for some applications. A Booth (1951) multiplier, on the other hand, offers simplicity and flexibility, by both breaking a multiplication up into pieces, and by allowing the size of the pieces to be chosen. Unfortunately, Booth multipliers become difficult to design for higher radices. The use of a fast adder tree, such as that found in a reduced area multiplier, permits straightforward design of very high radix Booth multipliers. Increasing the radix of a Booth multiplier in this manner results in large increases in speed with reasonable hardware cost. >

A BiCMOS dynamic carry lookahead adder circuit for VLSI implementation of high-speed arithmetic unit

Abstract: A BiCMOS dynamic carry lookahead circuit that is free from race problems is presented. A 16 b full-adder test circuit, which has been designed based on a 2 mu m BiCMOS technology, shows a more than five times improvement in speed as compared to the CMOS Manchester carry lookahead (MCLA) circuit. The speed advantage of the BiCMOS dynamic carry lookahead circuit is even greater in a 32- or 64-b adder. >

Performance Analysis of Fast Adders Using VHDL

Abstract: This paper presents performance analysis of different Fast Adders. The comparison is done on the basis of three performance parameters i.e. Area, Speed and Power consumption. Further, we present a design methodology of hybrid carry lookahead/carry skip adders (CLSKAs). This modified carry skip adder is modeled by using both fix and variable block size. In conventional carry skip adder, each block consists of ripple carry adder and skip logic is used after each block to generate carry for next block. The speed of operation depends on carry propagation from previous block to next block. In CLSKAs, we use carry lookahead logic in each block to generate carry for next block. The modified carry skip adders presented in this paper provides better speed and power consumption as compare to conventional carry skip adder and other adders like ripple carry adder, carry lookahead adder, Ling adder, carry select adder. The modified carry skip adders with fix block require few more CLB’s because of Carry lookahead logic, whereas with variable block scheme, area optimization is achieved.

The circuit design of multiple-valued logic voltage-mode adders

Abstract: Novel quaternary half adder, full adder, and a carry-lookahead adder are introduced. The proposed circuits are static and operate in voltage-mode. Moreover, there is no current flow in steady states, and thus no static power dissipation. Although the comparison in transistor count shows that the proposed quaternary circuits are larger than two respective binary ones, benefits in parallel addition arise from the use of multiple-valued logic. Firstly, the ripple-carry additions are faster because the number of carries are half compared to binary ones and the delay from the input carry through the output carry is relatively small. Secondly, the carry-lookahead scheme exhibits less complexity, which leads to overall reduction in transistor count for addition with a large number of bits.