Topic
Carry-lookahead adder
About: Carry-lookahead adder is a research topic. Over the lifetime, 243 publications have been published within this topic receiving 3794 citations.
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21 Jan 1986TL;DR: In this paper, an improved scheme for generating a carry lookahead is described, where large bit groups are used in the middle and shorter bit groups at the ends, providing for a reduction in carry propagation delay.
Abstract: An improved scheme for generating a carry lookahead is described. An irregular grouping, wherein large bit groups are used in the middle and shorter bit groups are used at the ends, provides for a reduction in carry propagation delay.
32 citations
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TL;DR: In this article, the implementation of an 8-bit multiplier design employing CMOS full adders, full adder using Double Pass Transistor (DPL) and multi-output carry Lookahead logic (CLA) is addressed.
32 citations
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06 Mar 2014TL;DR: In Very Large Scale Integration (VLSI) designs, Parallel prefix adders (PPA) have the better delay performance and these adders' delay, power and area are investigated and compared finally.
Abstract: In Very Large Scale Integration (VLSI) designs, Parallel prefix adders (PPA) have the better delay performance This paper investigates four types of PPA's (Kogge Stone Adder (KSA), Spanning Tree Adder (STA), Brent Kung Adder (BKA) and Sparse Kogge Stone Adder (SKA)) Additionally Ripple Carry Adder (RCA), Carry Lookahead Adder (CLA) and Carry Skip Adder (CSA) are also investigated These adders are implemented in verilog Hardware Description Language (HDL) using Xilinx Integrated Software Environment (ISE) 132 Design Suite These designs are implemented in Xilinx Virtex 5 Field Programmable Gate Arrays (FPGA) and delays are measured using Agilent 1692A logic analyzer and all these adder's delay, power and area are investigated and compared finally
32 citations
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TL;DR: The quantum carry-lookahead (QCLA) adder proposed in this paper can be used within current modular multiplication circuits to reduce substantially the run-time of Shor's algorithm.
Abstract: We present an efficient addition circuit, borrowing techniques from the classical carry-lookahead arithmetic circuit. Our quantum carry-lookahead (QCLA) adder accepts two n-bit numbers and adds them in O(log n) depth using O(n) ancillary qubits. We present both in-place and out-of-place versions, as well as versions that add modulo 2^n and modulo 2^n - 1.
Previously, the linear-depth ripple-carry addition circuit has been the method of choice. Our work reduces the cost of addition dramatically with only a slight increase in the number of required qubits. The QCLA adder can be used within current modular multiplication circuits to reduce substantially the run-time of Shor's algorithm.
31 citations
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TL;DR: This paper presents a fast binary adder in static CMOS realization that adds two 32-bit operands in 3.28 ns, measured from the assertion of the input to the arrival of the slowest sum bit.
Abstract: This paper presents a fast binary adder in static CMOS realization. While the carry derivation is similar to that in a conditional-sum adder, the proposed adder is also similar to that of a spanning tree carry lookahead adder in the sense that only selected carry bits are generated and the sum bits are produced by carry-select adders. In a 1.2 /spl mu/m static CMOS realization, the proposed adder adds two 32-bit operands in 3.28 ns. This delay is measured from the assertion of the input to the arrival of the slowest sum bit.
31 citations