Cascode

About: Cascode is a research topic. Over the lifetime, 5048 publications have been published within this topic receiving 52746 citations.

CMOS Analog Circuit Design

Abstract: 1.1 ANALOG INTEGRATED CIRCUIT DESIGN 1.2 NOTATION, SYMBOLOGY AND TERMINOLOGY 1.3 ANALOG SIGNAL PROCESSING 1.4 EXAMPLE OF ANALOG VLSI MIXED-SIGNAL CIRCUIT DESIGN 2.1 BASIC MOS SEMICONDUCTOR FABRICATION PROCESSES 2.2 THE PN JUNCTION 2.3 THE MOS TRANSISTOR 2.4 PASSIVE COMPONENTS 2.5 OTHER CONSIDERATIONS OF CMOS TECHNOLOGY 3.1 SIMPLE MOS LARGE-SIGNAL MODEL (SPICE LEVEL 1) 3.2 OTHER MOS LARGE-SIGNAL MODEL PARAMETERS 3.3 SMALL-SIGNAL MODEL FOR THE MOS TRANSISTOR 3.4 COMPUTER SIMULATION MODELS 3.5 SUBTHRESHOLD MOS MODEL 3.6 SPICE SIMULATION OF MOS CIRCUITS 4.1 MOS SWITCH 4.2 MOS DIODE/ACTIVE RESISTOR 4.3 CURRENT SINKS AND SOURCES 4.4 CURRENT MIRRORS 4.5 CURRENT AND VOLTAGE REFERENCES 4.6 BANDGAP REFERENCE 5.1 INVERTERS 5.2 DIFFERENTIAL AMPLIFIERS 5.3 CASCODE AMPLIFIERS 5.4* CURRENT AMPLIFIERS 5.5* OUTPUT AMPLIFIERS/BUFFERS 6.1 DESIGN OF CMOS OP AMPS 6.2 COMPENSATION OF OP AMP 6.3 DESIGN OF TWO-STAGE OP AMPS 6.4 POWER-SUPPLY REJECTION RATIO OF TWO-STAGE OP AMPS 6.5 CASCODE OP AMPS 6.6 SIMULATION AND MEASUREMENT OF OP AMPS 6.7 MACROMODELS FOR OP AMPS 7.1 BUFFERED OP AMPS 7.2 HIGH-SPEED/FREQUENCY OP AMPS 7.3 DIFFERENTIAL-OUTPUT OP AMPS 7.4 MICROPOWER OP AMPS 7.5 LOW NOISE OP AMPS 7.6 LOW VOLTAGE OP AMPS 8.1 CHARACTERIZATION OF A COMPARATOR 8.2 TWO-STAGE, OPEN-LOOP COMPARATOR DESIGN 8.3 OTHER OPEN-LOOP COMPARATORS 8.4 IMPROVING THE PERFORMANCE OF OPEN-LOOP COMPARATORS 8.5 DISCRETE-TIME COMPARATORS 8.6 HIGH-SPEED COMPARATORS APPENDIX A CIRCUIT ANALYSIS FOR ANALOG CIRCUIT DESIGN APPENDIX B INTEGRATED CIRCUIT LAYOUT APPENDIX C CMOS DEVICE CHARACTERIZATION APPENDIX D TIME AND FREQUENCY DOMAIN RELATIONSHIP FOR SECOND-ORDER SYSTEMS

A fast-settling CMOS op amp for SC circuits with 90-dB DC gain

Abstract: A technique that combines the high-frequency behavior of a single-stage op amp with the high DC gain of a multistage design is presented. This technique is based on the concept that a very high DC gain can be achieved in combination with any unity-gain frequency achievable by a (folded-) cascode design. Bode-plot measurements for an op amp realized in a 1.6- mu m process show a DC gain of 90 dB and a unity-gain frequency of 116 MHz (16-pF load). Settling measurements with a feedback factor of 1/3 show a fast single-pole settling behavior corresponding to a closed-loop bandwidth of 18 MHz (35-pF load) and a settling accuracy better than 0.03%. This technique does not cause any loss in output voltage swing. At a supply voltage of 5.0 V an output swing of about 4.2 V is achieved without loss in DC gain. The above advantages are achieved with a 30% increase in chip area and a 15% increase in power consumption. >

A high-swing, high-impedance MOS cascode circuit

Abstract: A simple cascode with the gate voltage of the cascode transistor being controlled by a feedback amplifier called a regulated cascode is presented. In comparison to the standard cascode circuit, the minimum output voltage is lower by about 30 to 60% while the output conductance and the feedback capacitance are lower by about 100 times. An analytical large-signal, small-signal, and noise analysis is carried out. Some applications like current mirrors and voltage amplifiers are discussed. Experimental results confirming the theory are presented. >

Cascode voltage switch logic: A differential CMOS logic family

Abstract: A differential CMOS Logic family that is well suited to automated logic minimization and placement and routing techniques, yet has comparable performance to conventional CMOS, will be described. A CMOS circuit using 10,880 NMOS differential pairs has been developed using this approach.

Evaluation and Application of 600 V GaN HEMT in Cascode Structure

Abstract: Gallium nitride high electron mobility transistor (GaN HEMT) has matured dramatically over the last few years. A progressively larger number of GaN devices have been manufactured for in field applications ranging from low power voltage regulators to high power infrastructure base-stations. Compared to the state-of-the-art silicon MOSFET, GaN HEMT has a much better figure of merit and shows potential for high-frequency applications. The first generation of 600 V GaN HEMT is intrinsically normally on device. To easily apply normally on GaN HEMT in circuit design, a low-voltage silicon MOSFET is in series to drive the GaN HEMT, which is well known as cascode structure. This paper studies the characteristics and operation principles of a 600 V cascode GaN HEMT. Evaluations of the cascode GaN HEMT performance based on buck converter at hard-switching and soft-switching conditions are presented in detail. Experimental results prove that the cascode GaN HEMT is superior to the silicon MOSFET, but it still needs soft-switching in high-frequency operation due to considerable package and layout parasitic inductors and capacitors. The cascode GaN HEMT is then applied to a 1 MHz 300 W 400 V/12 V LLC converter. A comparison of experimental results with a state-of-the-art silicon MOSFET is provided to validate the advantages of the GaN HEMT.