Showing papers on "Channel length modulation published in 1974"

Drain voltage limitations of MOS transistors

Abstract: A comprehensive investigation has been carried out into the factors which influence the maximum drain voltage of an M.O.S. transistor for normal pentode-like operation. The drain voltage is limited by two principal mechanisms, namely punch-through of the drain depletion region to the source, and breakdown, due to impact ionization in the high field region at the drain edge. A two-dimensional analysis technique for determining the drain voltage at the onset of either punch-through or avalanche breakdown, from a solution of Poisson's equation within the substrate depletion region, is described. The solutions are obtained using finite difference numerical methods which take into account the gate-induced potential profiles at the edge of the source and drain junctions. Boundary conditions of zero effective gate bias and channel current are imposed which simplify the solution of Poisson's equation to an electrostatic one. The punch-through voltage VPT is defined as the drain-to-source voltage at which the longitudinal field at any point along the edge of the source region inverts in sign to permit the drift of minority carriers from source to drain. Breakdown voltage, VBD, however, is determined by the drain voltage at which the maximum field in the device reaches the critical value for avalanche multiplication. Good agreement is achieved between theoretical and practical results for both mechanisms on a wide variety of devices. It is shown that VPT decreases as the channel length and substrate doping concentration decrease and as the oxide thickness and diffusion depth increase. VBD, however, decreases as the channel length, oxide thickness and diffusion depth decrease. Punch-through and breakdown are discussed for gate bias conditions above and below threshold. The sharp fall in breakdown voltage as the gate bias rises above threshold is explained on the basis of injected charge from the channel into the drain depletion region.

MOS current limiting output circuit

Abstract: An MOS push-pull driver circuit includes a pull up MOSFET and a pull-down MOSFET coupled to an output node A polycrystalline silicon current limiting resistor is connected between the drain of the pull-up MOSFET and the supply voltage conductor to provide a closer tolerance output current than is normally feasible for state-of-the-art MOSFET manufacturing processes

MOSFET's in the 0°K approximation: Static characteristics of MOSFET's in the 0°K approximation☆

Abstract: The static electrical characteristics below current saturation of MOSFET's with degenerate source and drain regions are calculated for operation at 0°K. The expression for current takes the same form as at room temperature although the flat-band voltage and the voltage across the depletion region at threshold are altered slightly. Potential hills occur in the channel if the gate does not overlap source and drain or if the oxide thickness is increased in the overlap regions. Although these barriers do not affect operation appreciably at room temperature, at 0°K a finite drain voltage (source-drain threshold voltage) is required to initiate conduction. This threshold voltage is included in the theory and the theory is compared with experimental results on p -channel enhancement mode MOSFET's at 4·2°K using hole mobility in the channel as a matching parameter. The channel hole mobility (assumed constant along the channel) is found to be relatively independent of gate voltage but to increase with increasing (negative) drain voltage. Values ranging between 500 and 1000 cm 2 /V-sec are deduced for drain voltages ranging from −1·2 V to −7 V. This compares to channel hole mobility values of 200–300 cm 2 /V-sec at room temperature. It is found that the channel width is on the order of 30–50 A—appreciably less than that at room temperature.

Design of short-channel ion-implanted mosfets with relatively deep junctions

Abstract: This paper discusses design considerations for short-channel ion-implanted MOSFET devices with relatively deep junctions. Four device parameters are considered: threshold and transconductance reduction, sub-threshold turn-on, and punch-through. Channel-length variations affect power and performance tolerances of enhancement/ depletion logic NOR gates in two ways: first, down-level current is inversely proportional to channel length; second, short-channel physical effects cause variations in transconductance and threshold voltage. It will be demonstrated that threshold and transconductance variations in short-channel devices tend to offset one another so their net contributions to tolerances on such circuit parameters as switching speed, down-level power and down-level voltage are negligible. Dual-energy ion implantation is used in the channel regions — a shallow implant to control threshold voltage, and a deep implant to control punch-through voltage. Hence high-resistivity (15 ohm-cm) substrates can be used to reduce junction capacitance. These implants are shown to have little effect on short-channel properties other than punch-through because the doses are low. Low channel doping and the relatively deep junctions contribute to a desirable, steep device turn-on characteristic. We concluded that short-channel effects do not have to be avoided in the design of small MOSFET devices. Using ion implantation and careful design, circuit tolerances can be maintained allowing parameters such as junction depth to be optimized for other criteria such as metallurgy compatibility.

Substrate current-a device and process monitor

Abstract: Typical characteristics of an n-channel, enhancement-mode, insulated-gate field effect transistor (IGFET) are shown in Figure 1. The drain current is plotted against the drain voltage for different values of the gate voltage. It can be seen from the figure that, after saturation is reached, the drain current increases again as the drain voltage is further increased. This additional current is attributed to the substrate current and can be measured simultaneously in the substrate lead.

Magnetic Sensitivity of Junction Field Effect Transistors with Uniform Channel Current Density

Abstract: MOS field effect transistors with two additional diffused contacts in the channel region were studied by Rao and Carr. The present work provides detailed theoretical analysis for an n-channel Junction Field Effect Transistor with a rectangular geometry. The variation of the Hall voltage with the drain to source voltage was plotted.