Showing papers on "Channel length modulation published in 1978"

A charge-sheet model of the MOSFET

Abstract: Intuition, device evolution, and even efficient computation require simple MOSFET (metal-oxide-semiconductor field-effect transistor) models. Among these simple models are charge-sheet models which compress the inversion layer into a conducting plane of zero thickness. It is the purpose of this paper to test one such charge sheet model to see whether this approximation is too severe. This particular model includes diffusion which is expected to be important in the subthreshold and saturation regions. As a test the charge sheet model is applied to long-channel devices. Long-channel MOSFET behavior has been thoroughly studied, and is very well explained by the Pao-Sah double-integral formula for the current. Hence, a clear-cut test is a comparison of the charge sheet model with the Pao-Sah model. We find the charge sheet model has two advantages over the Pao-Sah model. (1) It leads to a very simple algebraic formula for the current of long-channel devices. The same formula applies in all regimes from subthreshold to saturation. Neither splicing nor parameter changes are needed. No discontinuities occur in either the current or the small-signal parameters, or in the derivatives of the small-signal parameters. (2) It is simpler to extend the charge sheet model to two or three dimensions than the Pao-Sah model. This simplification is a result of dropping the details of the inversion layer charge distribution. An important aspect of the gradual channel approximation is brought out by the analysis. Suppose the boundary condition relating the quasi-fermi level at the drain, φfL, to that at the source, φfo, namely φ ƒL =φ ƒ0 +V D where VD is the drain voltage, is applied in all bias regimes. Then it is shown that this means the potential at the drain end of the channel, φsL is not related to the potential at the source end of the channel, φso, by φ sL =φ s0 +V D Instead, φsL is computed, not imposed as a boundary condition. It is suggested that this failure of the potential to satisfy the boundary condition at the drain is justifiable. That is, φsL should be reinterpreted as the potential at the point in the channel where the gradual channel approximation fails. Hence, (2) may be relaxed. However, the “channel length” in the gradual-channel approximation now becomes a fitting parameter and is not the metallurgical source-to-drain separation. In addition several aspects of the long-channel MOSFET are brought out: (1) Pinch-off is achieved only asymptotically as the drain voltage tends to infinity. This is in marked contrast to the often-stated, textbook view that pinch-off is achieved for some finite drain voltage, the saturation voltage. (2) The channel or drain conductance approaches zero only asymptotically. (3) The transconductance saturates only asymptotically. Figures comparing the simple charge-sheet model formulas with the usual textbook formulas are included for direct-current vs drain voltage, channel conductance vs drain voltage, and transconductance vs drain voltage. The charge-sheet model agrees with the original Pao-Sah double-integral formula for the current at all gate and drain voltages, and possesses the correct subthreshold behavior. The textbook formulas do not.

Subthreshold conduction in MOSFET's

Abstract: The dependence of channel current in subthreshold operation upon drain, gate, and substrate voltages is formulated in terms of a simple model. The basic results are consistent with earlier approaches for long-channel devices. For short-channel devices, the variation of current with drain voltage up to the punch-through voltage is accurately described. The threshold voltage of a short-channel device as a function of applied voltages follows as a natural result of the derivation. Results are presented which confirm the theory over a wide range of drain and gate voltages. With the application of substrate bias it is concluded from the data and the theory that two-dimensional effects can cause dramatic increases in the drain conductance.

A normally-off type buried channel MOSFET for VLSI circuits

Abstract: This paper presents the performance of a buried channel MOSFET (BC-MOSFET) that uses the bulk region as the conducting channel in contrast with the surface channel of the conventional device. Normally-off characteristic has been realized with the p-type silicon gate and the ion-implanted n-channel layer. Fabricated short channel BC-MOSFETs with the gate lengths of 1-3 µ have shown a small shift of threshold voltage with changing the gate length or drain bias. These devices also have high carrier mobility of 750 cm2/v.s and high breakdown voltage compared with those of the conventional device. Minimum delay time of 180 ps was obtained with a 13 stage ring oscillator which was constructed with 1 µ BC-MOSFET.

Optimization of nonplanar power MOS transistors

Abstract: Analysis of fundamental MOSFET parameters predicts device limits in high-voltage high-speed operation that exceed the performance of bipolar devices. The optimization of voltage, speed, and "on" resistance parameters for power MOSFET's suggests a vertical three-terminal device design with short, wide channels; a wide, lightly doped drain region; and field terminator rings at the device perimeter. Utilizing this design philosophy, VMOS transistors have been produced with source-drain breakdown voltage greater than 450 V, and 5.5-Ω "on" resistance for 2.0-mm2active area. With a high channel width packing density design and 2.5-mm2active area, a 30-V transistor has also been produced having only 0.060-Ω "on" resistance. The breakdown voltage and "on" resistance of these devices exceed the performance of other power MOSFET's currently available. Also, the switching speed of these devices (better than 15 ns) far exceeds the performance of high-voltage bipolar transistors. Measurements of drain leakage current at 200-V drain potential show a resistance ratio R_{off}/R_{on} of approximately 1010for a 20-V variation in gate-to-source voltage.

Method for fabricating transistor structures having very short effective channels

Abstract: A method, including a sequence of process steps, for fabricating insulated gate field effect transistors having very short effective channel lengths. In a first version of the method, the source and drain regions of the device are opened in one process step and self-alignment of the source and the drain to the gate is achieved in one masking step. The drain region is then masked and the source side of the channel is implanted to adjust the threshold voltage of the high threshold voltage channel region. In a second version of the method, the source region is opened and self-aligned with the gate prior to the opening of drain region. Implantation to adjust the threshold voltage of the high threshold voltage channel region takes place before the drain region is opened, and then the drain region is opened and self-aligned with the gate in a further masking step. In either version, the threshold voltage is adjustable and the channel length is controlled to be a small value.

Static induction transistor

Abstract: In a static induction transistor of the type wherein carriers are injected from a source region to a drain region across a potential barrier induced in a current channel, and wherein the height of the potential barrier can be varied in response to a gate bias voltage applied to a gate to thereby control the magnitude of a drain current of the transistor. The product of the channel resistance R c and the true transconductance (G m ) of the transistor is maintained less than one and the product of the true transconductance and the series resistance R s of the transistor is maintained greater than or equal to one in the main operative state of the transistor. The series resistance R s is the sum of a resistance of the source, a resistance from the source to the current channel, and the channel resistance from the entrance of the current channel to the position of maximum value (extrema point) of the potential barrier in the current channel. This static induction transistor has the advantage that the current-voltage characteristic curve is nearly linear over a very wide range of drain current including the low drain current region.

An analysis of the concave MOSFET

Abstract: The electrical characteristics of the concave MOSFET are analyzed by the two-dimensional numerical method and the theoretical result is in reasonable agreement with the experimental result. Even if the channel length of the concave MOSFET is short, the obtained current-voltage characteristics of the concave MOSFET are quite similar to those of the long-channel normal MOSFET and can be approximated by the normal MOSFET formula. In short-channel concave MOSFET's, the threshold voltage lowering due to the short-channel effect is not observed. It is observed that the threshold voltage of the concave MOSFET depends strongly on the substrate bias voltage as compared with the long-channel normal MOSFET. These observed results are followed by the two-dimensional numerical analysis. The increase of the punch-through breakdown voltage as well as that of the surface induced avalanche breakdown voltage of the concave MOSFET is predicted theoretically. The equivalent circuit model of the concave MOSFET is shown and discussed.

Characterization of the MOSFET Operating in Weak Inversion

Abstract: Publisher Summary This chapter describes the physical properties of the interface between silicon and silicon dioxide in metal-isolator semiconductor transistors and of their influence on the channel current of a MOS transistor, particularly in weak inversion. The channel current consequently, is several orders of magnitude smaller than in the normal operating region and is easily influenced by the nonuniformities in the vicinity of the interface. In order to be able to derive the properties of the interface from the measured weak-inversion current, one has to calculate the theoretical current flowing through the corresponding ideal transistor. To that end, it is necessary to characterize the experimental transistor as accurately as possible. This is done by means of three-terminal capacitance measurements that yield the channel length and the capacitances between different parts of the MOS transistor. The chapter discusses the accurate model for the drain current in a MOSFET, determination of the surface state density from the drain current versus drain voltage measurements in weak inversion, and influence of potential fluctuations on the mobility in weak inversion.

Entirely diffused vertical channel jfet: theory and experiment

Abstract: The experimental electrical properties of a vertical channel JFET fabricated by a double diffusion technique are presented. A table showing its principal characteristics for different values of the diffusion depths is included. The analysis of the “triode-like” operation revealed by the output characteristics is based on a two-dimensional numerical simulation of the device. At high drain currents ID is proportional to VDSα (α<1). This behaviour can be attributed mainly to the effect of channel length modulation by the drain voltage. At low drain currents, the potential barrier between the source and the drain determines the current magnitude. This is an exponential function of the barrier height which increases almost linearly when VGS increases and decreases non-linearly when VDS increases.

Twin channel Lorentz coupled depletion width modulation effect magnetic field sensor

Abstract: A high sensitivity, low noise, broad bandwidth, twin channel conduction Lorentz channel coupled semiconductive field sensor device is described. The conductive channels are configured to create exceptionally narrow, undepleted conduction zones of approximately filamentary form. The filamentary conductive channels so formed are provided with a common source at one end of each channel and a separate drain at the other end thereof. The independent drains are spaced apart by a narrow area of semiconductive material. Magnetic fields may be utilized to create a Lorentz voltage in a region between the two conductive channels to vary the amount of current received at the two drains by utilizing the depletion width modulation effects of the Lorentz voltage upon the boundaries defining the conductive channel portions. Modulation of the depletion zone widths and depths along the channel sides effectively move the streams of carriers and the conductive channel areas to conduct more current to one drain more than another. This develops a differential drain current balance which can be utilized to provide an output signal. Width and length criteria for defining the filamentary channel structures are described for the ultimate desired configuration and size which are to be obtained. As noted, operation of the device is based upon Lorentz voltage modulation of the width and depth of the depletion zone boundaries defining the conductive channel. The Lorentz voltage is created in an area of semiconductive material coupling the two filamentary channels. An increased signal output is obtained by reducing the width of the filamentary channels to eliminate excess carriers normally found in wide channel devices and, further, by making the depletion zones as large a portion of the total channel widths as can be obtained.

MOSFET switching device with charge cancellation

Abstract: A MOSFET switching device, including first and second control terminals; a first MOSFET having its gate connected to the first control terminal; a second MOSFET having its gate connected to the second control terminal and its source and drain both connected to the source of the first MOSFET; and a third MOSFET having its gate connected to the second control terminal and its source and drain both connected to the drain of the first MOSFET When complementary control signals are applied to the first and second control terminals, charge spikes occurring at the source and drain of the first MOSFET when the conduction state of the first MOSFET is changed are cancelled by charge spikes occurring simultaneously in the second and third MOSFET's

Anomalous drain current in n-MOSFET's and its suppression by deep ion implantation

Abstract: Effects of the deep ion implantation on the characteristics of the short channel n-MOSFET have been investigated by two-dimensional numerical analysis and verified experimentally. By the analysis, it has been found that the anomalous drain current which flows in the relatively deep region between the source and the drain has been effectively suppressed by the deep ion implantation of acceptor impurities into the channel region. Structure of short channel n-MOSFET with deep ion-implanted layer has been optimized by computer simulation to suppress the anomalous drain current. Experimentally, the low and steep subthreshold current characteristics have been obtained by deep ion implantation for short channel n-MOSFETs with L EFF = 1.2µm. Furthermore, the back gate bias dependence of the threshold voltage of the implanted short channel device can be made almost likely to that of the unimplanted long channel device.

Long-tailed-pair connections of MOSFET's operated in sub-threshold region

Abstract: Long-tailed pair connections of MOSFET's are used as voltage comparators, the input stages of operational amplifiers, and other circuitry where their nearly infinite gate impedances can reduce the loading upon preceding circuitry. As conventionally operated, the tail current caused to flow through the interconnected source electrodes of the MOSFET's is sufficient to bias them such that their source-to-gate voltages exceed a threshold voltage, and the input voltage offset error of the long-tailed MOSFET pair is likely to be higher than that of most long-tailed bipolar transistor pairs. By selecting a tail current that is sufficiently small to operate a long-tailed MOSFET pair such that their source-to-gate voltages are in the sub-threshold region, the MOSFET's exhibit exponential drain current versus source-to-gate characteristics which result in markedly reduced input offset voltage error.

Analog-to-digital converter employing constant-current circuit incorporating MISFET

Abstract: The constant-current circuit consists of two MISFETs connected in series and a gate bias circuit for these MISFETs. The drain voltage of the first MISFET is maintained substantially constant by the source voltage of the second MISFET. The first MISFET does not sustain the channel length modulation, because its drain voltage is substantially constant. Consequently, a constant output current is obtained through the drain of the second MISFET.

Modeling the operation of the n-channel deep-depletion SOS/MOSFET

Abstract: We present a model for the n-channel deep-depletion SOS/MOSFET which is valid over its entire operating range. This model, which is suitable for incorporation in a circuit simulation program, accurately predicts the source-to-drain current for device operation in depletion and in both weak and strong accumulation. Important aspects of the theory are 1) incorporation of the effect of the depth dependence of mobility in thin SOS films by computing accumulation layer thickness, 2) use of a computationally efficient approximation for silicon surface potential in accumulation, 3) inclusion of carrier velocity saturation effects on drain saturation potential, and 4) prediction of drain current in saturation through analysis of the velocity-saturated region of the channel. Verification of the model is achieved by comparing predicted drain current to that measured from test transistors of varying channel lengths (2.5-7.5 µm) and manufacture. The procedures used to obtain the model parameters from these devices are also included.

Changes in effective channel length due to hot-electron trapping in short-channel m.o.s.t.s

Abstract: Stressed operation of p-channel mosts in the pre-avalanche region can cause the injection of hot electrons into the gate oxide adjacent to the source and drain junction Trapping of this injected charge causes a localised reduction of the threshold voltage near the stressed junction and a consequent reduction of the effective channel length Measurement of the saturated output conductance shows that the Early effect is much reduced after selective charge trapping The phenomenon can be explained by regarding the stressed transistors as a composite device consisting of a number of series-connected mosts with differing threshold voltages, and can be used deliberately to reduce short-channel effects in small mosts

Current controlling semiconductor device

Abstract: The semiconductor device has a zone of a first conduction type including a channel zone with low concentration of dissociation centres. Current input and output electrodes are connected to the channel ends; and a control electrode near the channel applies to it a control voltage generating a depletion layer and defining the current channel in the channel zone.The channel zone has such a width and concentration of dissociation centres, that when a forward control voltage is applied, the channel is pinched off producing a potential barrier in the channel zone for charge carriers moving from the electrodes during the transistor main operating state. The height of the barrier is capacitively controlled by the voltage applied to the drain