Showing papers on "Channel length modulation published in 1982"

Short-channel MOST threshold voltage model

Abstract: A new short-channel threshold voltage model based on an analytic solution of the two-dimensional Poisson equation in the depletion region under the gate of an MOS transistor (MOSTs) is presented. A simple closed-form expression for the variation of threshold voltage as a function of drain voltage, substrate bias, channel length, oxide thickness, and channel doping is derived. An exponential dependence on channel length and a linear dependence on drain and substrate biases is prediced for the reduction in the short-channel threshold voltage. These results are in qualitative and quantitative agreement with simulated and experimental results reported in literature. The predictions for the threshold voltage and subthreshold drain current are in close agreement with measured characteristics of MOS transistors down to submicron dimensions. The closed-form expressions for the threshold voltage and subthreshold drain current are well suited for circuit simulation and for determining performance limits of MOSTs.

An accurate and simple MOSFET model for computer-aided design

Abstract: Presents accurate device models (8-10 percent) to describe the drain-current characteristics of short-channel (>1 /spl mu/m) enhancement mode devices (EMD) and ion-implanted depletion-mode devices (DMD). The primary emphasis is on model accuracy and simplicity of formulation. The model form allows efficient extraction of model parameters resulting in accurate description of measured data. Also discussed is a derivation of the model equations with emphasis on a carrier mobility expression which includes the effects of surface scattering, channel scattering, and substrate bias. The effect of intrinsic source and/or drain series resistance on the carrier mobility is also included. The lowering of drain current due to bulk charge in the substrate and current modulation due to short and narrow channel effects and implicitly embedded in the models.

An accurate JFET/MESFET model for circuit analysis☆☆☆

Abstract: An accurate model for junction field-effect transistors (JFETs) and for Schottky barrier field-effect transistors (MESFETs) with micron and submicron dimensions is presented. The following effects are modeled: distributed channel charge, electrostatic drain feedback, drift velocity saturation, channel length modulation, substrate bias effect, subthreshold region effect, short-length and narrow-width effects, drain-source punch-through, variable capacitance effects, and temperature effects. It is primarily physical rather than empirical and only one set of parameters is needed to simulate devices of a particular technology. The model is intended for silicon devices, but the extension to devices in semiconducting III – V compounds and with insulating substrates is straightforward. The model is compared to experimental data.

Miniaturization of Si MOSFET's at 77 K

Abstract: Micrometer and submicrometer dimension Si MOSFET's have been studied at liquid nitrogen temperature. The emphasis of the study has been on the changes in the minimum channel length required for long-channel behavior L min due to cooling. It is found that there is a reduction in L min which is quite considerable in MOSFET's with low-channel doping. We have shown that this effect is due to a shorter lateral depletion width, and therefore longer effective channel length at low temperatures. A drastic decrease in punchthrough current has also been observed.

An improved method to determine MOSFET channel length

Abstract: An accurate and simple method to determine channel length and parasitic drain/source series resistance is presented. This method is based on measured data of two identical devices with different channel lengths. Because of its simplicity, the technique is suitable for use in automatic parameter testing systems.

Accumulation-punchthrough mode of operation of buried-channel MOSFET's

Abstract: The current-voltage characteristics of a buried-channel MOSFET operated in a "punchthrough-accumulation" mode, when the neutral implanted channel is completely depleted due to punchthrough by substrate bias and an accumulation layer is induced by the gate, are demonstrated. It is shown that the value of one of the device model parameters, φ MS , used under the above mode of operation corresponds to the gate and the substrate rather than to the gate and the channel.

A new method to electrically determine effective MOSFET channel width

Abstract: A new, easy, and accurate electrical measurement method for determining process bias of MOSFET channel width is proposed. This method is based on the linear relationship between the effective width and the channel conductance (or drain current) of a MOSFET operating in the linear region. Constant and sufficiently high gate voltages compared with the threshold voltage of the device are used in the measurement to minimize the error due to the threshold-voltage variation with W in narrow-width devices. The validity of the method is supported by identical results obtained using different gate voltages.

A simple model for short-channel effects of a buried-channel MOSFET on the buried insulator

Abstract: A majority-carrier distribution model and a channel potential-profile model, in which the barrier-lowering effect is taken into account, are proposed for a buried-channel MOSFET (BC-MOSFET/ SOI). Simple expressions for threshold voltage and drain breakdown voltage were derived from the models for a short-channel BC-MOSFET/ SOI. The comparison between theory and experimental results shows reasonable agreement. The drain-bias coefficient γ of threshold voltage for BC-MOSFET's/ SOI is approximately proportional to TN D -1L eff -2, where T, N D , and L eff are the temperature, the doping concentration in the channel region, and the channel length, respectively. The coefficient γ depends slightly on the drain bias. BC-MOSFET's/SOI are able to be more miniaturized than surface-channel MOSFET's (SC-MOSFET's) at the small power source voltage, and SC-MOSFET's are able to be more miniaturized than BC-MOSFET's/SOI at the large drain bias. It is shown that the conventional, simple scaling scheme, which holds the constant electric field, is not applicable to BC-MOSFET's/SOI. The power source voltage has to be fixed when dimensions and doping concentrations are scaled down. On the other hand, only the channel region thickness has to be fixed when the power source voltage is scaled down.

A geometrical model of the threshold voltage of short and narrow channel MOSFETs

Abstract: A simple geometrical model allows the calculation of the threshold voltage of short and narrow channel MOSFETs as a function of gate length, gate width, source and drain depth, substrate voltage and source drain voltage. Input parameters of the program are the customary values such as oxide thickness and, furthermore, an effective impurity concentration in the field region. The flat band voltage and the effective impurity concentration in the channel region can be calculated by a modified SUPREM program.

A closed-form threshold voltage expression for a small-geometry MOSFET

Abstract: An analytical expression is developed to predict the threshold voltage of a small-geometry MOSFET. The expression includes the effects of field doping encroachment at the channel edges, and charge sharing with the source and drain regions.

A Closed-Form Threshold Voltage Expression for a Small-Geometry MOSFET

Abstract: An analytical expression is developed to predict the threshold voltage of a small-geometry MOSFET. The expression includes the effects of field doping encroachment at the channel edges, and charge sharing with the source and drain regions.

Equivalent circuit for telephone choke coil - uses MOSFET exhibiting drain current when gate-source voltage is zero

Abstract: The equivalent circuit uses a MOSFET exhibiting a high breakdown voltage with its voltage threshold adjusted by ion implantation in the channel region, so that a drain current is present when the gate/source voltage is zero. The gate and substrate terminals of the MOSFET are coupled to the drain or source. The MOSFET is connected between the wires of a telephone line via two service resistors either side of it. The junction between each resistor and the MOSFET is connected to earth via a pair of opposing Zener diodes connected in series. A pair of series spark gaps are also connected across the lines, with the junction between them coupled to earth. The circuit can deal with voltages of 800 volts across the speech wires and voltages of 1200 volts between each speech wire and earth.

A novel BBD structure for low voltage operation

Abstract: A new MOS BBD which can operate at extremely low voltage has been realized. A novel pentode MOS structure, having three overlapping gates, has been developed by introducing double poly-Silicon process. Making potential gradient along the channel length and excluding the stray capacitance, high transconductance and low channel length modulation are simultaneously obtained, and as a result, the transfer inefficiency is decreased. Consequently, the transfer inefficiency of 2\times10^{-5} has been obtained even at 1.5V supply and 40kHz clock.

Simple and accurate size calculation of MOS transistor

Abstract: The letter describes an analytical solution to the problem of finding a correct size of a MOS transistor required to charge a load capacitance to a wanted voltage level within a given time. The resultant formula is extremely simple, yet very accurate. It could be utilised by an LSI designer, as well as in automatic design algorithms. The expression for the channel width over channel length ratio was derived from the second-order drain current equations for both regions, saturated as well as linear (not from simplified, first-order approximations).

Two-dimensional analysis of hot-electron emission current in MOS FET

Abstract: There has been growing concern about degradation in MOSFET characteristics due to hot-electron emission into the gate oxide as device dimensions are scaled down. This paper reports on a two-dimensional analysis of hot-electron emission. The emission current is related to the electric field and current distribution in a MOSFET for the purpose of identifying the factors contributing to its increase with device miniaturization. A variety of MOSFET structures, such as conventional, LDD, and double-diffused MOSFETs are analyzed and compared. The analysis on a conventional MOSFET clarifies that the major factor contributing to the increase in hot-electron emission in a small-size MOSFET is the surface electric field intensity near the drain. This implies that the impurity distribution in the diffused drain has a great influence. The numerical analysis shows that the electric field near the drain is decreased in LDD and double-diffused structures. For a given device size, the impurity density in the lightly doped portion of the drain can be properly chosen to homogenize the drain electric field, resulting in drastic reduction in hot-electron emission current.

Nonuniform displacement of MOSFET channel pinchoff

Abstract: The effects of fixed, positive oxide charge under the gate on the characteristics of MOSFET devices are well known. But the combined effects of the oxide charge in the field and of the edge contour and impurity profile on the device characteristics have not been as extensively investigated in the past. In this paper we address this problem and show results which give a new insight in the performance of MOSFET devices. With the help of two-and three-dimensional numerical solutions of Poisson's equation, it was found that this oxide charge lowers the threshold potential resulting in an increase in conductivity towards the two edges of the channel along the width direction. As a consequence, the geometric channel pinchoff locus shifts towards the drain as the channel edge is approached. This is in contrast to the conventional assumption of the pinchoff locus being in parallel to the drain.