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Showing papers on "Channel length modulation published in 1983"


Journal ArticleDOI
TL;DR: In this paper, the feasibility of double diffused drain is investigated comparing it with a conventional As drain over a wide range of effective channel length from 0.5 to 5 µm.
Abstract: An As-P(n+-n-) double diffused drain is characterized as one of the most feasible device structures for VLSI's from the overall viewpoint of device design. This device makes good use of both As, suitable for microfabrication, and P, in realizing a graded junction. The feasibility of this double diffused drain is investigated comparing it with a conventional As drain over the wide range of effective channel length from 0.5 to 5 µm. We have also succeeded in directly measuring hot-hole gate current as low as on the order of 10-15A. This current seems to have an important influence on the hot-carrier effects. On the basis of the experiments and simulations using the two-dimensional process/device analysis programs SUPREM and CADDET, it is shown that this device structure provides remarkable improvements, not only in terms of channel hot-electron effects, but also avalanche hot-carrier effects, which are more responsible for hot-carrier related device degradation due to impact ionization at the drain. In addition, this structure has almost the same short channel effect characteristics, for example threshold-voltage lowering as a conventional MOSFET.

88 citations


Journal ArticleDOI
TL;DR: In this paper, the behavior of hot-electron gate and substrate currents in very short channel devices was studied and an empirical relationship between the effective electron temperature and the field was found to be T e = 9.05 × 10-3E.
Abstract: The behaviors of the hot-electron gate and substrate currents in very short channel devices were studied. For a test device with electrical channel length of 0.14 µm, the hot-electron substrate current can be detected at 0.9-V drain voltage which is lower than the silicon band gap. The gate current can be measured at 2.35-V drain voltage, which is lower than the oxide-silicon energy barrier for electrons. These measurements support the quasi-thermal-equilibrium approximation and suggest that the hot-electron-induced problems cannot be eliminated in future VLSI MOSFET's of arbitrarily short channels by reducing the drain bias below some constant critical energies. An empirical relationship between the effective electron temperature and the field is found to be T e = 9.05 × 10-3E.

74 citations


Journal ArticleDOI
TL;DR: In this article, a new grooved-gate MOSFET with its drain separated from channel implanted regions (DSC structure) is proposed for the purpose of obtaining higher breakdown voltages: drain sustaining voltage and highest applicable voltage placed by hot-carrier effects.
Abstract: A new grooved-gate MOSFET with its drain separated from channel implanted regions (DSC structure) is proposed for the purpose of obtaining higher breakdown voltages: drain sustaining voltage and highest applicable voltage placed by hot-carrier effects. Nonimplanted regions between channel implanted and source/drain regions are a unique feature of this device structure. The self-aligned nonimplanted region in the channel is obtained by using silicon dioxide and resist overhangs. These overhangs are fabricated by grooving the silicon substrate. The DSC structure helps reduce the electric field at the drain. Characteristics of experimental devices are presented and compared with those of conventional MOSFET's, from the viewpoint of overall VLSI device design. This device structure is shown to provide remarkable improvements, achieving a 3- or 4-V increase in drain sustaining voltage, as well as a 1- or 2-V increase in the highest applicable voltage as limited by hot-electron injection. In addition, the proposed device can alleviate such short-channel effects as V th lowering, and in particular, diminish narrow-channel effects. The influence of nonimplanted length on breakdown voltage is also clarified using the CADDET, two-dimensional analysis program.

41 citations


Journal ArticleDOI
T. Yamaguchi1, S. Morimoto
TL;DR: In this article, a comparison of the electrical characteristics of small geometry p-channel and n-channel MOSFET's with and without field implantation leads to the conclusion that the field implantations is the main cause of the narrow-channel-width effect on threshold voltage, threshold-voltage increase and drain current degradation.
Abstract: Electrical characteristics of small geometry p-channel and n-channel MOSFET's are characterized based on an analytical model that includes short-channel, narrow-channel, and carrier-velocity-saturation effects. Theoretical results on threshold voltage, threshold-voltage shift by a substrate bias voltage, and drain current are in good agreement with the experimental results over wide ranges of channel lengths from 1 to 9 µm and channel widths from 2 to 14 µm. A comparison of the electrical characteristics of MOSFET's with and without field implantation leads to the conclusion that the field implantation is the main cause of the narrow-channel-width effect on threshold-voltage increase and drain-current degradation. The carrier-velocity-saturation effect starts to appear at the 3-µm channel length for the n-channel device and at 1 µm for the p-channel device under 5-V operation. According to the theoretical analysis of a 1-µm-channel inverter circuit, a CMOS inverter has superior noise immunity with 1.4 to 2.0 times larger driving-current capability in a load MOS device and requires 9 percent less area than a 1-µm n-channel enhancement/depletion inverter.

37 citations


Journal ArticleDOI
TL;DR: In this article, a model for the drain I-V characteristics is proposed and a related model incorporating conductivity modulation that predicts linear relationships between the substrate and the collection currents and the drain current in this region of operation.
Abstract: When a short-channel MOSFET is driven into the avalanche-induced breakdown region, the drain current increases rapidly and usually shows a snapback characteristic. Both the substrate current and the current collected by a nearby reverse-biased p-n junction also increases with increasing drain current in this region of operation. All of these effects are associated with minority-carrier injection from the source junction into the substrate. A model for the drain I-V characteristics is proposed. Also presented is a related model incorporating conductivity modulation that predicts linear relationships between the substrate and the collection currents and the drain current in this region of operation. Experimental results agree well with the models.

37 citations



Journal ArticleDOI
TL;DR: Small-geometry buried-channel depletion MOSFETs (BCD-MOSFets) are characterized based on an analytical model that includes short-channel, narrow- channel, and carrier-velocity saturation effects andoretical results on drain current are in good agreement with experimental results.
Abstract: Small-geometry buried-channel depletion MOSFETs (BCD-MOSFETs) are characterized based on an analytical model that includes short-channel, narrow-channel, and carrier-velocity saturation effects. The drain current is calculated based on the surface electrons induced by the gate-bias voltage and the buried-channel junction FET. The narrow-channel effect is modeled not only by the additional depletion-layer charges created by a fringing-field effect in the field region, but also by the effective channel width as a function of gate-bias voltage. Surface-electron mobility is modeled as a function of the vertical and lateral electrical fields created by the gate-bias and drain voltages, while bulk-electron mobility is described as a function of the lateral electric field due to the drain voltage. Theoretical results on drain current are in good agreement with experimental results.

10 citations


Patent
18 May 1983
TL;DR: In this article, the authors proposed a method to improve the imperfect transfer efficiency of the BBD by a method wherein the concentration of drains is lowered particularly than as in the past, and dependence upon a voltage of a drain and source current of the MOSFET is reduced.
Abstract: PURPOSE:To improve the imperfect transfer efficiency of the BBD by a method wherein the concentration of drains is lowered particularly than as in the past, and dependence upon a voltage of a drain and source current of the MOSFET is reduced. CONSTITUTION:When the concentration at the channel part of a P type substrate is designated as nA, and concentration at the N type drain 28 is designated as nD, and when nD becomes to the 10 times or more of nA, reduction of width WP of a depletion layer to extend to the substrate side becomes to a little, and when nD is made as the same grade or less with nA, width of the depletion layer to extend to the channel part is suppressed, dependence upon the voltage VDS (channel length modulation) of the drain and source current IDS is suppressed, and the imperfect transfer efficiency alphaD can be improved sharply. Moreover, sources and drains of the two FET's connected in cascade connection are coupled with an N type layer to attain reduction of diffusion resistance. When the device is formed in a multistage type by this constitution to make the FET's to be the fittest, the imperfect transfer efficiency alphaj depending upon a time constant according to ON resistance and the electric charge accumulation capacity of the FET is not also aggravated, and reduction of the driving voltage and enhancement of the frequency characteristic can be attained together.

6 citations


Journal ArticleDOI
TL;DR: In this paper, the asymmetrical behavior of hot-electron modified MOSFET's with respect to swapping of source and drain is due to two-dimensional effects taking place within the transition region separating the device channel from the terminal junctions.
Abstract: This brief shows how the asymmetrical behavior of hot-electron modified MOSFET's with respect to swapping of source and drain is due to two-dimensional effects taking place within the transition region separating the device channel from the terminal junctions. In particular experimental data concerning enhanced threshold-voltage shift, asymmetrical transconductance, anomalous body effect, as well as short-channel-like behavior exhibited by the stressed transistors, are presented and discussed.

6 citations


Patent
20 Jul 1983
TL;DR: In this article, the static induction transistor (SIT) is modified to serve as a substitute of any conventional bipolar transistor in a given circuitry, where the gate-to-gate distance and the impurity concentration of the channel region of an SIT are selected so that the channel is pinched off by the depletion layer at a predetermined forward gate bias.
Abstract: The new kind of field effect transistor having a non-saturating characteristic, i.e. static induction transistor (SIT), proposed by the present inventor is modified to serve as a substitute of any conventional bipolar transistor in a given circuitry. That is, the gate-to-gate distance and the impurity concentration of the channel region of an SIT are so selected that the channel is pinched off by the depletion layer at a predetermined forward gate bias. When the forward gate bias applied is below a certain level, the drain current will increase fundamentally exponentially with an increase of the drain voltage above some threshold voltage, whereas when the gate bias applied is above the certain value, the drain current will increase rapidly with a small increase in the drain voltage.

6 citations