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Showing papers on "Channel length modulation published in 1985"


Proceedings ArticleDOI
01 Jan 1985
TL;DR: In this paper, the design of DI-LDD submicron channel devices is investigated, specifically focusing on the halo optimization for punchthrough and threshold falloff protection, and a two dimensional numerical analysis is used to demonstrate the tradeoff between breakdown voltage and improved short channel threshold fall off as the Halo concentration is increased.
Abstract: The design of DI-LDD submicron channel devices is investigated, specifically focusing on the halo optimization for punchthrough and threshold falloff protection. Two dimensional numerical analysis is used to demonstrate the tradeoff between breakdown voltage and improved short channel threshold falloff as the halo concentration is increased. For a given halo doping level, there is a maximum permitted drain voltage for each channel length which is limited by avalanche breakdown, drain induced threshold lowering and punch-through. A window of useful halo doses is established from 5\times10^{16} to about 8\times10^{17} below which there is no significant improvement of the device and above which there is an unacceptable level of device degradation. A maximum V ds versus channel length curve for the polysilicon gate DI-LDD MOSFET is obtained which implies that power supply voltage must be scaled by approximately the same factor as channel length for this type of device.

80 citations


Journal ArticleDOI
TL;DR: In this article, the principal parameters for short-channel MOSFETs were derived from the experimental curves ID(VG) and ID(VD) curves. But the main assumption is that the devices fabricated on the same silicon chip have the same technological reduction of transistor channel length and the same series resistance of source and drain.
Abstract: In this paper we present a new method of determining the principal parameters for short-channel MOSFET modelling: VT, μ0, θ, ΔL and RSD. They are deduced from the experimental curves ID(VG) (for small drain voltages) and ID(VD) (for relatively large gate voltages) curves. The main assumption is that the devices fabricated on the same silicon chip have the same technological reduction of transistor channel length and the same series resistance of source and drain. Our method takes advantageously into account (a) a new accurate determination of the threshold voltage and (b) the variation of the low-field mobility with channel length. Results obtained by applying this method to short-channel devices are given and discussed.

61 citations


Journal ArticleDOI
TL;DR: In this paper, an n+n-double-diffused drain MOS transistor was used to suppress hot-carrier emission. But the results of the optimum drain impurity profile to give the minimum channel electric field are obtained when the maximum lateral electric field is located at the boundary between the P region and the As region.
Abstract: Channel electric field reduction using an n+-n-double-diffused drain MOS transistor to suppress hot-carrier emission is investigated. The double-diffused structure consists of a deep low-concentration P region and a shallow high-concentration As region. The channel electric field strongly depends on such process and device parameters as the length of the n-diffusion region, drain junction depth, gate oxide thickness, gate length, applied voltage, and P implant energy. The optimum condition for a double-diffused structure is determined based on those parameter dependences of the channel electric field. The results of the optimum drain impurity profile to give the minimum channel electric field are obtained when the maximum lateral electric field is located at the boundary between the P region and the As region. The hot-carrier immunity of MOSFET and test circuits are improved by two orders of magnitude and one order of magnitude, respectively, under the optimum conditions.

40 citations


Journal ArticleDOI
TL;DR: In this article, a two-dimensional device simulator is developed to investigate the effects of velocity overshoot on Si MOSFETs, in which electron temperature-dependent mobility is determined as a function of electron-gas temperature.
Abstract: A new two-dimensional device simulator is developed to investigate the effects of velocity overshoot on Si MOSFET's An electron temperature-dependent mobility model, in which mobility is determined as a function of electron-gas temperature, is used in the simulator Marked velocity overshoot occurs in the vicinity of the drain edge of MOSFET's and makes the potential barrier height at the source edge lower for ultrashort-channel MOSFET's Therefore, velocity overshoot effects appear not only as degradation of electron transit time but also as increased drain current as compared with the case in which drift velocity does not overshoot The increase in drain current depends strongly upon low-field mobility and bias conditions and appears for channel lengths shorter than 1000 nm When low-field mobility is higher than 500 cm2/V s and channel length is 100 nm, the increase in drain current is more than 15 times for bias conditions of strong inversion and a lateral electric field of more than 105V/cm in the vicinity of the drain edge

36 citations


Journal ArticleDOI
TL;DR: In this article, the channel length and series resistance of MOSFETs are determined by taking two-dimensional geometry effects in order to extract parameters which are physically meaningful, and new techniques which take these effects into account are proposed.
Abstract: Several techniques have been proposed to determine the channel length and series resistance of MOSFET's. Numerical simulations show that these algorithms must carefully account for two-dimensional geometry effects in order to extract parameters which are physically meaningful. New techniques which take these effects into account are proposed for extracting the channel length and series resistance.

33 citations


Journal ArticleDOI
TL;DR: In this paper, a device model that predicts large-signal GaAs MESFET performance has been implemented on the large-scale circuit simulation program SPICE, taking into consideration drift velocity saturation, channel length modulation, and subthreshold current effects.
Abstract: A device model that predicts large-signal GaAs MESFET performance has been implemented on the large-scale circuit simulation program SPICE. The model takes into consideration drift velocity saturation, channel length modulation, and subthreshold current effects. In addition, the model depends primarily on physical (i.e. material and geometric) rather than empirical parameters. Combined with the SPICE program, a general CAD tool is formed which can be used to aid in the design of GaAs circuits such a power amplifiers, oscillators, mixers, and fast-switching digital integrated circuits. Model predictions are compared to measured device performance, and limitations of this large-signal circuit design approach are discussed.

27 citations


Journal ArticleDOI
TL;DR: In this paper, a four-terminal model for a long-channel depletion-mode MOS transistor including both the diffusion and the drift components of the current along the channel is developed.
Abstract: A four-terminal model for a long-channel depletion-mode MOS transistor including both the diffusion and the drift components of the current along the channel is developed. The theory, which is derived in the gradual channel hypothesis, has been built-up by considering both Poisson's equation and the current-continuity equation. The model is able to describe, without discontinuities, the dc drain current in the enhancement, depletion, and subpinchoff regimes of operation of the device. It is shown that pinchoff and zero drain conductance are naturally achieved as the drain voltage increases, while in the subpinchoff regime the drain current exponentially depends on gate voltage and is mainly due to the diffusion component. Finally, it is found that mobility degradation effects due to the normal component of the electric field can easily be taken into account and it is shown that experimental data favorably compare with the proposed model.

24 citations


Journal ArticleDOI
TL;DR: In this article, the temperature coefficient of the threshold voltage in long buried-p-channel MOSFET is 2.02 mV/°C, which is much larger than that in the long enhancement-mode n-channel MCM.
Abstract: The temperature coefficient of the threshold voltage in long buried-p-channel MOSFET is dV_{th}/dT = 2.02 mV/°C, which is much larger than that in the long enhancement-mode n-channel MOSFET (-1.27 mV/°C). The difference is caused by the charge freeze-out phenomenon in the buried-channel MOSFET. The absolute value of the temperature coefficient of the threshold voltage |dV_{th}/dT| , decreases with decreasing channel length in the n-channel MOSFET, however, it increases with decreasing channel length in the submicrometer p-channel MOSFET. The difference results from the majority-carrier spill-over phenomenon in the buried-p-channel MOSFET.

23 citations


Journal ArticleDOI
TL;DR: In this article, the authors investigated hot-electron-induced degradation of transconductance and threshold voltage at 77 K of n-channel enhancement metal-gate MOSFET's as a function of electrical stress applied at liquid nitrogen temperature.
Abstract: Hot-electron-induced degradation of transconductance and of threshold voltage at 77 K of n-channel enhancement metal-gate MOSFET's was investigated as a function of electrical stress applied at liquid nitrogen temperature. After stress, the threshold voltage was found to have increased at low drain voltages but to have remained unchanged at higher drain voltages, and the saturation transconductance was virtually unchanged for operation in the normal mode. For operation in the inverse mode (source and drain interchanged), the threshold voltage was found to have increased, independent of drain voltage, while the saturation transconductance was decreased. The threshold voltage for inverted operation increased monotonically with stress time, while the saturation transconductance decreased initially and then saturated. This saturation corresponds to an order of magnitude decrease in carrier mobility in the channel near the drain. These results are interpreted using a model in which the threshold voltage and channel mobility are position-dependent. While hot-electron-induced degradation may not be a problem for devices operated only in the forward saturation region, it could be a serious problem for devices such as bilateral switches.

19 citations


Journal ArticleDOI
TL;DR: In this article, an analytic one-dimensional model for lightly doped drain (LDD) MOSFET devices is presented, where the voltage drops in the n-source and drain, including both IR and voltage drop across the depletion region of the drain were calculated analytically.
Abstract: An analytic one-dimensional model for lightly doped drain (LDD) MOSFET devices is presented. This model decomposes the LDD device into an intrinsic MOSFET in series with n-source and drain diffusion. A conventional charge control model with a pseudo two-dimensional approach was used to calculate the current flow in the intrinsic MOSFET. The voltage drops in the n-source and drain, including both IR drops and voltage drop across the depletion region of the drain were calculated analytically. By reconstructing all the voltage drops across contact, source/drain, and channel regions, the calculated drain currents as a function of terminal voltages agree well with experimental data. Device optimization is also presented by using this analytical model for "full" LDD and As-P double diffused LDD structures.

19 citations


Journal ArticleDOI
TL;DR: In this paper, a simple but general model for explaining the series resistance dependence of transconductance and field effect mobility is developed, which enables a quantitative analysis of series resistance effects on the maximum mobility and the corresponding gate voltage, has been successfully tested on short channel MOSFETs with various channel lengths and external series resistances.
Abstract: A simple but general model for explaining the series resistance dependence of transconductance and field-effect mobility is developed in the letter. This model, which enables a quantitative analysis of series resistance effects on the maximum mobility and the corresponding gate voltage, has been successfully tested on short-channel MOSFETs with various channel lengths and external series resistances.

Journal ArticleDOI
TL;DR: In this paper, a simple CAD model is proposed for the short-channel enhancement-mode MOSFET, which possesses continuity of current, transconductance and output conductance throughout the triode, and saturation ranges of operation.
Abstract: A simple CAD model is proposed for the short-channel enhancement-mode MOSFET. The conventional use of drain bias modulation of channel length to describe saturation characteristics has been discarded and replaced by drain bias enhancement of channel velocity. The model possesses continuity of current, transconductance and output conductance throughout the triode, and saturation ranges of operation. It has been tested against experimental transistors and against two-dimensional numerically simulated transistors, and has given satisfactory results in all cases. The model is based on good physics, is easy to understand, is straightforward to use, and is computationally efficient.

Journal ArticleDOI
TL;DR: In this paper, the authors used a two-dimensional finite-element model of a MOSFET with no free parameters and compared it with four self-aligned silicon-gate n-channel transistors with channel lengths of 0.80, 1.83, 2.19, and 8.17 µm.
Abstract: When short-channel MOSFET transistor models are compared to experimental data, the uncertainty in some of the physical input variables often requires that some of the input variables be adjusted to fit the data. This uncertainty is increased by a lack of knowledge of process sensitivity information on critical parameters. These uncertainties have been eliminated using a two-dimensional finite-element model of a MOSFET with no free parameters. The model is compared to four self-aligned silicon-gate n-channel MOSFET's with channel lengths of 0.80, 1.83, 2.19, and 8.17 µm. The 0.80, 1.83, and 8.17-µm devices have phosphorus sources and drains. The 2.19-µm device has an arsenic source and drain. These devices span the range of channel lengths from a short-channel device, totally dominated by velocity saturation and source-drain profile shape, to a long-channel device, well characterized by a long-channel model. Using the data obtained from the measurements described in this work, it is possible to model the drain current for all of the transistors studied without adjustable parameters. Transistors with 0.80-µm channel length differ in model input from those with 8.17-µm channel length only in the length of the polysilicon gate. If sufficiently accurate parameters are available, these methods allow the characteristics of submicrometer transistors to be predicted with ±5-percent accuracy. These simulations show that the observed short-channel effects can be accounted for by existing mobility data and a simple empirical model of these data. Triode and saturation effects are dominated by two-dimensional drain field penetration of the channel region. Subthreshold effects are caused by distortion of fields in the entire channel region by the drain field.

Patent
Christopher F. Codella1, Seiki Ogura1
12 Jul 1985
TL;DR: In this article, a self-aligned GaAs, lightly doped drain metal-semiconductor field effect transistor (disclosed) is presented, which consists of a shallow n- active channel region (53A) formed on a GaAs substrate (50), a Schottky gate (54) overlying the n- region and highly doped and deep n* source (64) and drain (65) regions formed on either side of the gate.
Abstract: Disclosed is a self-aligned GaAs, lightly doped drain metal-semiconductor field effect transistor. The device (70) consists of a shallow n- active channel region (53A) formed on a GaAs substrate (50), a Schottky gate (54) overlying the n- region and highly doped and deep n* source (64) and drain (65) regions formed on either side of the gate. In the channel regions between the gate edges and the source/drain regions are positioned n-type source/drain extensions (57A, 58A) which have an intermediate depth and doping concentration to minimize the device series resistance, suppress short channel effects and permit channel length reduction to submicron levels. In addition, p-type pockets (59A, 60A) are provided under the source/drain extensions (57A, 58A) to better control the device threshold voltage and further reduce the channel length.

Journal ArticleDOI
Tiao-Yuan Huang1
TL;DR: In this paper, the effect of hot-electron effects on transistors with funnel-shaped channel regions was studied in terms of hot electron effects and it was suggested that future transistor design could take advantage of this effect in obtaining optimum hotelectron-resistant transistors.
Abstract: Transistors with funnel-shaped channel regions are studied in terms of hot-electron effects. Experimental results indicate that funnel-shaped transistors are more resistant to hot-electron effects when operating with the wider-channel region close to the drain. It is suggested that future transistor design could take advantage of this effect in obtaining optimum hot-electron-resistant transistors.

Journal ArticleDOI
TL;DR: In this paper, a buried-gate MOSFET was proposed for submicrometer devices, especially for 1/4 micrometer level devices, and the results of two-dimensional device simulation indicate that the buried gate shows less substrate current than conventional MOS-FET for low gate voltages and different gate voltage dependence of the substrate current.
Abstract: A buried-gate MOSFET is proposed for submicrometer devices, especially for 1/4 micrometer level devices. In this structure, reduced short channel effects are shown and very shallow junctions are not required. The results of two-dimensional device simulation indicate that the buried-gate MOSFET shows less substrate current than conventional MOSFET for low gate voltages and different gate voltage dependence of the substrate current.

Journal ArticleDOI
TL;DR: In this paper, the effect of channel length on the two regions of the characteristic (i.e., in the neighborhood of the first and second peaks) is investigated, where the substrate current at the first peak normalized to the drain current remains independent of the channel length.
Abstract: The substrate current versus gate voltage characteristic of short-channel LDD structures showed a second peak for large spacer widths and low n-concentrations. The effect of channel length on the two regions of the characteristic (i.e., in the neighborhood of the first and the second peaks) is investigated. While the substrate current at the first peak normalized to the drain current remains independent of the channel length, the normalized substrate current at the second peak increases as the channel length decreases. These observations are explained on the basis of the drain depletion region extended beyond the gate edge. A previously published model by Ko et al. [4] was extended to an LDD structure to quantitatively explain this phenomena.

Journal ArticleDOI
TL;DR: In this paper, the authors performed capacitance-voltage measurements on small-size MOSFETs with applied drain voltage to obtain information about hot-electron effects.
Abstract: Capacitance-voltage measurements were performed on small-size MOSFET's with applied drain voltage to obtain information about hot-electron effects. The theoretical analysis shows that hot carriers cause remarkable changes 1) in the vertical and horizontal distribution of the electrons in the inversion layer, 2) in the surface potential drop, 3) in the depletion charge, and 4) in the effective threshold voltage. The influence of these hot-electron effects on the channel current is discussed.

Journal ArticleDOI
TL;DR: A new empirical model for the threshold voltage of enhancement NMOSFET is proposed based on experimental observations and shows good agreement for transistors with effective channel length down to 1.8 μm and effective channel width down to1.0 μm.
Abstract: A new empirical model for the threshold voltage of enhancement NMOSFET is proposed based on experimental observations. This model covers both short and narrow channel effects. The model equation is formulated by the superposition of these two effects, and extraction of model parameters is presented. Comparison of the model with experimentally measured values shows good agreement for transistors with effective channel length down to 1.8 μm and effective channel width down to 1.0 μm.

Journal ArticleDOI
T.Y. Huang1, J.Y. Chen
TL;DR: In this paper, the double-hump effect in substrate current and associated enhanced gate current injection in FS-transistors when channel length and gate oxide are scaled down were investigated. And the authors found that floating-gate FS-tranistors with short-channel length and thin gate oxide were more efficient in programming when operating in wide-drain mode.
Abstract: n-channel transistors with a funnel-shape (FS) channel region were fabricated with thin gate oxide (21 nm) and short-channel length (1 µm) to study the effects of channel shapes on hot-electron effects. Two interesting phenomena are observed. First, the double-hump substrate current phenomenon is found when operating with wider channel close to drain side (wide-drain mode), while the narrow-drain mode shows the usual single-peak substrate current characteristics. Second, an enhanced gate current injection is found in the wide-drain mode, which is surprising as substrate current is actually lower in this mode. The finding is interesting as it suggests that floating-gate FS-tranistors with short-channel length and thin gate oxide are more efficient in programming when operating in wide-drain mode. This contradicts the previous SIMOS EPROM device that utilizes funnel-shape channel region operating in narrow-drain mode. The discrepancy is ascribed to the occurrence of double-hump effect in substrate current and associated enhanced gate current injection in FS-transistors when channel length and gate oxide are scaled down.

Journal ArticleDOI
TL;DR: In this paper, a simplified one dimensional model is studied to understand the transport phenomena of MOSFET's including the high field region, taking into account the average energy of electrons explicitly.
Abstract: A simplified one dimensional model is studied to understand the transport phenomena of MOSFET's including the high field region. The model takes into account the average energy of electrons explicitly. A remarkable change is observed in the field distribution in comparison with the conventional treatment without the hot-electron energy for channel length 1 μm and V G 〈V D . It is shown that the hot-electron energy results in a relative decrease of the field at the drain.

Journal ArticleDOI
01 Dec 1985
TL;DR: In this article, a model for the operation of MOS transistors which is applicable to many power and short channel devices is presented for the effects of the mobility reduction due to the gate-channel field and to velocity saturation of the channel carriers under the high drainsource field.
Abstract: A model is presented for the operation of MOS transistors which is applicable to many power and short channel devices. This improved 1-dimensional charge control model allows for the effects of the mobility reduction due to the gate-channel field and to velocity saturation of the channel carriers under the high drainsource field. Experiments have verified the model for n and p channel devices. The high drain voltage ID/VG data are compared with the model predictions using accepted experimental values of the bulk saturation velocity and velocity-field curves together with experimental measurements of the channel series resistance and the gate-field reduction of the mobility.

Journal ArticleDOI
G.C. Holmes1
TL;DR: In this paper, a curve tracer reveals a low-level current spike in the gate-source characteristic of enhancement-mode MOSFETs, and its use in measuring the threshold voltage at a vanishingly small channel current is described.
Abstract: A curve tracer reveals a low-level current `spike? in the gate-source characteristic of enhancement-mode MOSFETs. The origin of this spike is explained, and its use in measuring the threshold voltage of any MOSFET at a vanishingly small channel current is described. The technique also identifies whether the MOSFET is n-channel or p-channel, enhancement-mode or depletion-mode.

Patent
11 Jun 1985
TL;DR: In this article, the authors proposed a method to compensate the short channel effect of an MOS transistor by connecting the drain of a TR part with a large threshold value with the source of a TRS with a small threshold value, and connecting the gates of the TR parts in common.
Abstract: PURPOSE:To compensate the short channel effect of an MOS transistor (TR) by connecting the drain of a TR part with a large threshold value with the source of a TR part with a small threshold value, and connecting the gates of the TR parts in common. CONSTITUTION:An enhancement MOSTR11 and a depletion type MOSTR21 are connected in series to constitute a composite TR. Then a current is flowed from the TR21 to the TR11. This composite TR device corresponds to the short channel effect of the enhancement type or depletion type MOSTR. Consequently, the evil influence of a decrease in gain, variance in linearity and current ratio, etc., upon channel length modulation is all removed.