Showing papers on "Channel length modulation published in 1986"

Method of fabricating a MOSFET with graded source and drain regions

Abstract: A method of forming metal oxide semiconductor field-effect transistors (MOSFET) is described wherein the source and drain regions are disposed by ion implantation in a manner substantially perpendicular to the substrate surface in two steps, such that the concentration of impurities increases with lateral distance away from the gate electrode member to suppress the hot e injection, to prevent channeling effect, to increase punch through voltage and to increase gate-aided breakdown voltage.

On the accuracy of channel length characterization of LDD MOSFET's

Abstract: A comprehensive investigation into the various mechanisms that limit the accuracy of channel length extraction techniques for lightly doped drain (LDD) MOSFET's is presented. Analytic equations are derived to quantify the sensitivity of the extraction techniques to the geometry effect, and bias dependence of the n-source and drain resistance. The analytic approach is supplemented and verified by exercising channel length extraction algorithms on current-voltage characteristics obtained from rigorous numerical simulations of a variety of LDD MOSFET's. The analyses clearly show that low gate overdrives and consistent threshold voltage measurements are required to accurately extract the metallurgical channel length. The analytic equations can be used to project the limitations of channel length extraction methods for future submicrometer LDD MOSFET's.

Comparison of drain structures in n-channel MOSFET's

Abstract: Practical limitations in channel lengths for n-channel MOSFET'S under 5-V operation are discussed for conventional arsenic-drain, phosphorus-drain, phosphorus-arsenic double diffused drain (DDD), and lightly doped drain (LDD) structures. Process parameter dependence of device characteristics and optimal process conditions are also evaluated for each drain structure. It is clarified that the minimum usable channel length is about 0.7-µm, which is realized by the DDD and LDD devices. In these devices, the hot-carrier-induced device degradation is no longer a major restriction on minimum channel length, but the short-channel effect and the parasitic bipolar breakdown are dominant restrictions. The phosphorus drain with a shallow junction formed by rapid thermal annealing can expand the arsenic drain limitation.

Low-temperature mobility behaviour in submicron MOSFETs and related determination of channel length and series resistance

Abstract: The electron mobility behaviour in submicron MOSFETs is studied in the temperature range of 77–300 K. As the effective channel length is reduced, the effective mobility as well as the field-effect mobility are found to decrease and to become less temperature dependent. These experimental results are explained by the influence of series resistance and effective channel length, which are both temperature dependent. The possibility of accurate determination of series resistance and “pure” mobility is demonstrated. A new method is proposed to determine submicron MOSFET channel length at low temperatures.

A charge-sheet analysis of short-channel enhancement-mode MOSFETs

Abstract: A charge-sheet analysis of the short-channel MOSFET is presented. The expression achieved for the drain current, which takes into account both the drift and the diffusion components and also mobility degradation effects, holds in the strong-inversion, weak-inversion, and saturation regimes of the device operation, and results in a continuous function of all bias voltages. The model predicts an exponential dependence of the drain current on drain voltage in weak inversion and the threshold dependence on both channel length and drain voltage. Moreover, the proposed approach predicts results which satisfactorily compare with numerical simulations obtained from the two-dimensional analyzer MINIMOS and experimental data.

A new approach to threshold voltage modelling of short-channel MOSFETS

Abstract: A simple analytical model has been developed to predict the threshold voltage on drain bias dependence of an arbitrarily doped short-channel MOSFET. Based on an analytical solution of the two-dimensional Poisson equation, the potential distribution in the channel depletion region has been derived. The maximum surface field and the minimum surface potential are used to determine the threshold voltage. The influence of drain voltage on threshold voltage has been included by an equivalent shrinkage of the virtual channel length hereafter called “voltage-length transformation”. This simple but general procedure enables us to account for the drain effect and to extend other threshold voltage models derived under assumption of low drain-source voltage. Predictions for threshold voltage have been compared with results of two-dimensional numerical analysis and experimental data. The comparison has been made for a wide variety of doping profiles, channel length, substrate and drain bias, gate oxide thickness and junction depth. Excellent agreement has been obtained down to submicron channel length.

A measurement-based charge sheet capacitance model of short-channel MOSFET's for SPICE

Abstract: Based on the surface potential formulation[1], a charge-sheet capacitance model for short-channel MOSFET's has been developed and implemented in SPICE. No iterations are needed to find the surface potential. The model equations are charge-based and includes the drift velocity saturation, the diffusion current, the effect of the bulk charge, the channel length modulation and the channel side fringing field capacitances. As a byproduct of the development of this capacitance model, an analytic charge-sheet current model has been obtained. The current, charges, their first derivatives(conductance and capacitance) and second derivatives are continuous over all the operating regions. An automatic direct-on-wafer off-chip capacitance measurement system with 14 aF rms resolution has been developed for performing the model parameter extraction.

Method of fabricating an improved insulated gate semiconductor device

Abstract: To provide a MOSFET power switching device with a low on-resistance, the body regions of active MOSFET cells are formed through a pre-existing continuous high conductivity zone created immediately adjacent the surface of a common drain region. This zone retards the depth of diffusion of the cell body regions to achieve a shorter MOSFET channel length and also forms lower resistivity portions of the device main or forward current paths; both factors contributing a lowering of the device on-resistance.

A threshold voltage expression for small-size MOSFET's based on an approximate three-dimensional analysis

Abstract: A simple threshold voltage expression based on an approximate three-dimensional analysis has been obtained for MOSFET's with the LOCOS isolation structure. It predicts both the short-channel and the narrow-width effects on the threshold voltage of MOSFET's, and the results match the experimental data. In addition, the threshold expression is more general than any other existing models. It includes all the relevant device parameters, such as the drain voltage, the oxide and surface charges, and the fringe field through the oxide sidewalls.

Influence of drain-induced barrier lowering on the dynamic conductance of short-channel MOSFETs

Abstract: An analysis of the influence of drain-induced barrier lowering (DIBL) on the dynamic conductance of short-channel MOSFETs is presented. A new method of determination of surface state density Nss from the normalised dynamic conductance characteristics is proposed. The method is extended to the case of very short-channel devices to account for DIBL effects.

Short channel MOSFET

Abstract: A field effect transistor having operating characteristics based on the control and modulation of the punch through phenomenon. The channel region between the source and the drain regions is appropriately doped such that the source and drain depletion regions overlap when no potential is applied between source and drain. The overlapped region in the absence of a gate field has a potential barrier. A gate voltage modulates the barrier to below the kT/q parameter. The source-to-drain fields also modulate the barrier.

Drain-Induced Barrier Lowering In Short Channel Transistors

Abstract: Drain-induced barrier lowering (DIBL) [8.1]-[8.6] has been studied by many workers. The result of DIBL is an increase in the residual leakage current in short channel devices as the drain to source voltage is increased. Fig. 8.1 shows the measurement of the drain to source current of a short channel MOSFET’s, as a function of the drain bias, for gate bias of 0 V. Note that the current increases exponentially with drain bias. Fig. 8.2 shows the simulated potential profile between the source and drain of a long and short channel MOSFET’s, with a drain to source bias of 9 V. The potential barrier between the source and the channel is lowered by the drain bias, for the short channel device. The drain to source leakage current is exponentially dependent on the potential barrier. This leakage current can cause many problems in circuits such as dynamic memories or low power circuits in battery operation environments. In the first example, if the pass transistor of the one-transistor dynamic memory cell [8.7] has significant leakage current, then the bit information of the cell may be lost. In the case of low power circuits, leakage current in the devices means much larger standby power. If severe leakage problems are present, the circuit may not function properly, especially for NMOS circuits.

Mos type semiconductor device

Abstract: PURPOSE:To inhibit the channel length modulation dependent on drain voltage by a method wherein the substrate impurity concentration of an off-set gate structure is made equal to the impurity concentration of reverse conductivity type under a gate electrode or smaller than that. CONSTITUTION:The surface of a P substrate 4 with the impurity contration NA=10 -10 atom/cm is provided with N layers 5a, 6a, and 7a with the impurity concentration ND=10 -10 atom/cm , and the MOS capacitor part is provided with an n layer 8a of high concentration. Gate electrodes are provided on an SiO2 insulation film 9: (n) electrode 1a is connected to the electrode 3a of the MOS capacitor, which are connected to a clock signal line 10, whereas an electrode 1b and a capacitor electrode 3b are connected to a signal line 11, and an electrode 2a to a signal line 12, thus driving a BBD. Selecting the ND at a value approximately the same as that of NA or less than it causes the marked reduction in channel length modulation by the inhibition of the width Wp of a depletion layer spreading over the channel part; therefore, the incomplete transfer efficiency of the BBD device is largely improved.

Field effect transistor circuit arrangements

Abstract: of EP0051134A field effect transistor has operating characteristics based on the control and modulation of the punchthrough phenomenon as well as the space charge limited conduction of channel current. The channel region (20) between the source (22) and the drain (24) regions is appropriately doped p-type such that the depletion zones of the n doped source and drain regions overlap. In the absence of the gate field there is a potential barrier in the overlapped depletion zones high enough to prevent injection of electrons for channel conduction, and low enough to be modulated to below the kT/q barrier height criterion by the gate- and the source-to-drain fields. The actual barrier height potential is determined by the doping and channel length. When a positive voltage is applied to the gate, the gate field will cause the potential in the channel to be reduced much the same way as the external field affects an insulator. In addition to the gate field, the source-drain potential introduces a longitudinal field which also modulates and distorts the barrier. Alternative structures have an insulating substrate or a semiconductor substrate and buried semiconductor layer forming the barrier.