Showing papers on "Channel length modulation published in 1988"
TL;DR: In this paper, a charge-based large-signal transient model for the enhancementmode thin-film SOI MOSFET in strong inversion is presented, which is suitable for circuit simulators such as SPICE.
Abstract: A charge-based large-signal transient model for the enhancement-mode thin-film SOI MOSFET in strong inversion, suitable for circuit simulators such as SPICE, is presented. The model physically accounts for the predominant short-channel effects in MOSFET's (namely threshold-voltage reduction, drain-induced conductivity enhancement, velocity saturation with mobility degradation, and channel-length modulation) as influenced by the unique features of thin SOI devices (i.e. the presence of an additional back gate and the possibility of a floating film body). It includes a description of generation current due to (weak) impact ionization, which can have a far greater influence on SOI (as compared to bulk) MOSFET's due to the associated charging of the floating body. Measurements on devices of varied geometry show good agreement with model predictions. The model is implemented in SPICE2, to be used for circuit and device CAD, and TECAP, for automated parameter extraction. >
120 citations
01 Dec 1988
TL;DR: In this article, a simple method for characterisation of MOSFETs with appreciable source and drain series resistance is presented, where the ratio g/g 1/2m of conductance g and transconductance gm is shown to be a linear function of gate bias, whose intercept equals the threshold voltage and whose slope is proportional to the square root of the channel length.
Abstract: A simple method for characterisation of MOSFETs with appreciable source and drain series resistance is presented. The ratio g/g1/2m of conductance g and transconductance gm is shown to be a linear function of gate bias, whose intercept equals the threshold voltage and whose slope is proportional to the square root of the channel length. The method is illustrated using measurements on 0.4 ?m to 1.0 ?m channel length LDD transistors.
72 citations
TL;DR: In this article, an analytical threshold voltage model is developed based on the results from a three-dimensional MOSFET simulator, called MICROMOS, which is derived by solving Poisson's equation analytically and is used to predict the threshold voltage of MOS-FETs with fully recessed oxide isolation.
Abstract: An analytical threshold voltage model is developed based on the results from a three-dimensional MOSFET simulator, called MICROMOS. The model is derived by solving Poisson's equation analytically and is used to predict the threshold voltage of MOSFETs with fully recessed oxide isolation (the trench structure). Coupling was observed between the short-channel effect and the inverse-narrow-width effect. The coupling results from the mutual modulation of the depletion depth and is used to extend the analytical inverse narrow-width model to small-geometry devices. The model is compared with experimental data obtained from the literature as well as with the three-dimensional simulator. Satisfactory agreement for channel length down to 1.5 mu m and channel widths down to 1 mu m has been obtained. >
57 citations
TL;DR: In this paper, the authors measured channel hot-electron-generated substrate currents in MOSFET devices with channel lengths down to 0.09 mu m, and a family of characteristic plots of substrate current, normalized to drain current, I/sub SUB/I/sub D/, rather than (V/sub DS/V/ sub DSAT/)/sup -1/ was obtained.
Abstract: Channel hot-electron-generated substrate currents were measured in MOSFET devices with channel lengths down to 0.09 mu m, and a family of characteristic plots of substrate current, normalized to drain current, I/sub SUB//I/sub D/, rather than (V/sub DS/-V/sub DSAT/)/sup -1/ was obtained. For channel lengths greater than 0.5 mu m, the characteristics are independent of channel length. For channel lengths in the range of 0.15 mu m, the characteristics are independent of channel length. For channel lengths in the range of 0.15 mu m, the normalized substrate current at constant V/sub DS/ increases with decreasing channel length. However, as the channel length is decreased below 0.15 mu m, a decrease of the normalized substrate current is observed. The decrease is larger at 77 K than at 300 K. This decrease accompanies the onset of electron velocity overshoot over a large portion of the channel. It is suggested that the decrease is due either to a decrease of carrier energy because energy relaxation and transit times become comparable, to a relative decrease of the carrier population in the channel, or to both. >
57 citations
Patent•
24 Jun 1988
TL;DR: In this paper, a construction method and apparatus for lightly doped drain MOSFET that has low or minimum drift on-state resistance and maintains high voltage blocking in the off-state is presented.
Abstract: Construction method and apparatus for lightly doped drain MOSFET that has low or minimum drift on-state resistance and maintains high voltage blocking in the off-state. Temperature sensitivity of the electrical properties of the MOSFET are also reduced relative to MOSFETs produced by processes such as SIPOS. Voltage level shifting of p-channel and n-channel MOSFETs, produced according to the invention, relative to another voltage level is easily accomplished.
52 citations
TL;DR: The performance of ASIM under DC and transient conditions is evaluated by comparing the current and voltage at the terminals with that of detailed physical simulations and measurements.
Abstract: A description is given of ASIM (ATT i.e. the effects of mobility reduction, carrier velocity saturation, and channel length modulation are included in both. The ASIM model accounts for effects due to device dimensions and temperature. The performance of ASIM under DC and transient conditions is evaluated by comparing the current and voltage at the terminals with that of detailed physical simulations and measurements. The results agreed well with that of two-dimensional device simulations and measurements. >
49 citations
TL;DR: In this article, the degradation of 1- mu m-gate-length nMOSFET operating under normal biasing conditions at room temperature is analyzed and a physical model of hot-electron trapping in SiO/sub 2/ is developed and used with a two-dimensional device simulator (PISCES) to simulate the aging of the device.
Abstract: An analysis of the degradation of 1- mu m-gate-length nMOSFET operating under normal biasing conditions at room temperature is reported. A physical model of hot-electron trapping in SiO/sub 2/ is developed and is used with a two-dimensional device simulator (PISCES) to simulate the aging of the device under normal biasing conditions. The initial degradation takes place near the high-field drain region and spreads over a long time toward the source. The degraded I-V characteristics of the MOSFET exhibit a shift of the pinchoff voltage and a compression of the transconductance, for forward and reverse operation, respectively. The simulated degradation qualitatively agrees with reported experimental data. Large shifts of the MOSFET threshold voltage for small drain voltages result as the degradation is spreading toward the source. An inflection point arises for low gate and drain voltages in the drain I-V characteristics of the MOSFET. This inflection point originates when the pinchoff of the channel-induced trapped-electron charge is overcome by the drain voltage; the drain acts as a second gate (short-channel effect). The estimation of the device's lifetime by simulated aging is proposed. >
45 citations
TL;DR: In this paper, a two-dimensional analytical model for the threshold voltage of a short-channel MOSFET with a Gaussian-doped channel has been developed, where the Gaussian profile has been simulated by a novel integrable function.
Abstract: A two-dimensional analytical model for the threshold voltage of a short-channel MOSFET with a Gaussian-doped channel has been developed. The Gaussian profile has been simulated by a novel integrable function. This makes possible a purely analytical solution of the two-dimensional Poissons equation in the channel region of the MOSFET. >
32 citations
07 Nov 1988
TL;DR: An efficient dc MOSFET model is presented for accurate simulation of analog circuits and a new smoothing function is used to unify the linear and saturation regions in a single expression.
Abstract: This paper presents an efficient dc MOSFET model for accurate simulation of analog circuits. A new approach to model channel length modulation is presented. An empirical expression for channel length modulation is derived from measurements. This is used to model the observed behavior of g/sub D/ with gate, drain, and substrate bias. Some of the models commonly used for circuit simulation do not predict the effects of gate and substrate bias adequately. A new smoothing function is used to unify the linear and saturation regions in a single expression. Continuity of transconductance is maintained between the weak and strong inversion regions. Model efficiency is maintained by avoiding the use of transcendental functions in the smoothing techniques. We demonstrate >
30 citations
TL;DR: In this article, a new version of a pseudo-two dimensional analysis for the drain region of short channel MOSFETs is proposed, which guarantees the continuity of the output conductance and its derivative with respect to the drain voltage at the point of transition from the linear to the saturation region.
Abstract: A new version of a pseudo-two dimensional analysis for the drain region of short channel MOSFETs is proposed. Second order effects such as mobility degradation, velocity saturation, and short channel effects are included in the analysis and the dependence on the processing parameters is taken into consideration. The model proposed in this paper guarantees the continuity of the output conductance and its derivative with respect to the drain voltage at the point of transition from the linear to the saturation region. The predictions of the model are confirmed by a comparison with the experimental data available in the literature.
29 citations
TL;DR: The successful modeling of short-channel transistor breakdown characteristics with effective channel length down to 0.6 mu m is reported, the first successful application of a short- channel breakdown model in a circuit simulator.
Abstract: The successful modeling of short-channel transistor breakdown characteristics with effective channel length down to 0.6 mu m is reported. The sudden increase in the MOS drain current due to threshold voltage reduction caused by the forward biasing of the source-substrate junction is also modeled with considerable accuracy. This is the first successful application of a short-channel breakdown model in a circuit simulator. Model parameter extraction and installation of the model in the circuit simulator is also discussed. >
TL;DR: In this paper, a lightly doped drain (LDD) MOSFET can be decomposed as an intrinsic MOS-FET in series with n/sup -/ source and drain regions, and an expression for the drain noise power spectrum was developed in terms of terminal voltages.
Abstract: A lightly doped drain (LDD) MOSFET can be decomposed as an intrinsic MOSFET in series with n/sup -/ source and drain regions. Under the assumption that the 1/f noise mainly comes from the intrinsic MOSFET part of the device, an expression for the drain noise power spectrum was developed in terms of terminal voltages. Noise measurements were performed on n-channel devices with effective channel lengths varying from 0.87 to 11.37 mu m. Good agreement between experimental values and theoretical values for a device channel length shorter than 4 mu m was obtained. It was also found that the LDD device has less noise than a conventional-structured MOSFET with the same channel length and operated under same terminal voltages. >
Patent•
NEC1
TL;DR: In this article, the authors proposed an improved transistor arrangement for MIS circuits and the like, which is capable of stable operation without breakdown in the event of a surge voltage, and the current path through the protective transistor is largely confined to the central area of the channel region, preventing current from being concentrated at side portions of the Channel region adjacent the field oxide surrounding the transistor.
Abstract: The invention relates to an improved protective transistor arrangement for MIS circuits and the like which is capable of stable operation without breakdown in the event of a surge voltage The protective transistor has a channel region whose length varies along the width of the channel such that the channel length at the central portion of the channel region is made less than the channel length at the sides of the channel region By way of this construction, the current path through the protective transistor is largely confined to the central area of the channel region, preventing current from being concentrated at side portions of the channel region adjacent the field oxide surrounding the transistor
TL;DR: In this paper, the second-order effects in metaloxide-semiconductor field effect transistors (MOSFETs) are considered and a model of a MOS-FET including these considerations and emphasizing charge conservation is discussed.
Abstract: Second-order effects in metal-oxide-semiconductor field-effect transistors (MOSFETs) are important for devices with dimensions of 2 microns or less. The short and narrow channel effects and drain-induced barrier lowering primarily affect threshold voltage, but formulas for drain current must also take these effects into account. In addition, the drain current is sensitive to channel length modulation due to pinch-off or velocity saturation and is diminished by electron mobility degradation due to normal and lateral electric fields in the channel. A model of a MOSFET including these considerations and emphasizing charge conservation is discussed.
TL;DR: In this article, a simple theory to predict the threshold voltage variation of short-channel MOS transistors with substrate bias is proposed, which is based on vertical field perturbations due to the source-drain.
Abstract: A simple theory to predict the threshold voltage variation of short-channel MOS transistors with substrate bias is proposed. While the basis of the model is vertical field perturbations due to the source-drain, its uniqueness depends on a definition of threshold voltage based on the amount of total free charge in the channel rather than inversion of the entire channel. The theory has been verified for transistors of three channel lengths, namely 2.70, 1.70, and 0.70 mu m, fabricated with a p-well CMOS process. A comparison is made with an earlier model based on field perturbation. The validity of the arguments underlying the theory has been demonstrated by 2-D device simulations with MINIMOS. >
Patent•
NEC1
TL;DR: In this article, a gate electrode (21) covered with an insulating film (27 and 28′) intervenes between the source/drain regions, so that the channel region is increased in length.
Abstract: For preventing a field effect transistor from the short-channel effects, there is disclosed a field effect transistor comprising a channel region (28) and source/drain regions (22 and 23) deviating form the central portion of the channel region in the lateral direction of the field effect transistor, a gate electrode (21) covered with an insulating film (27 and 28′) intervenes between the source/drain regions, so that the channel region is increased in length.
01 Sep 1988
TL;DR: In this paper, the 3D effects of MOSFET's dute to the nonplanar nature of the field-oxide body have been investigated by MINIMOS 5.
Abstract: This paper presents 3D effects of MOSFET's dute to the nonplanar nature of the field-oxide body. The investigations have been carried out by MINIMOS 5 our fully three-dimenisional simiulatioin program. Three-dimensional effects like threshold shift for small channel devices, channel narrowinig and the enhanced conductivity at the channel edge have been successfully modeled.
TL;DR: In this paper, a simple model for the linear region of submicrometer n-channel MOSFETs is proposed in which the effective channel length of the device is considered as a function of applied gate and drain voltages, channel doping and temperature.
Abstract: A simple model for the linear region of submicrometer n-channel MOSFETs is proposed in which the effective channel length of the device is considered as a function of applied gate and drain voltages, channel doping and temperature. The MOSFET channel is supposed to have three regions with different values of surface state density and oxide charge to take into account the processing-induced damages at its edges. The model is compared with the experimental results on device transconductance at room and low temperatures. It allows an easy understanding of various results unaccounted for by standard models and offers a physical basis for more sophisticated modelling.
IBM1
TL;DR: In this paper, a method for the channel potential extraction of a MOSFET from the gate-to-drain capacitance is presented, which is demonstrated on two devices.
Abstract: A method for the extraction of the channel potential of a MOSFET from the gate-to-drain capacitance is presented. The method is demonstrated on two devices. Comparison is made between experimental results and numerical simulation. It is shown that a potential drop within the drain diffusion would reduce the actual voltage drop across the channel. A technique to account for this voltage drop is also given. >
TL;DR: In this paper, the transresistance r≡gm/g2 was used to measure the channel length of MOSFETs with arbitrary parasitic source-drain series resistance.
Abstract: We use the transresistance r≡gm/g2 to measure channel length of MOSFET's with arbitrary parasitic source-drain series resistance. The channel length error due to the bias dependence of series resistance is completely eliminated by extrapolation to zero gate drive. The final accuracy is limited by sourcedrain asymmetry and errors in threshold voltage measurement; measurements on 0.5 µm lightly-doped drain MOSFET's indicate it is about 3 nm and a factor of seven better than previous methods.
Patent•
12 May 1988
TL;DR: In this article, the same input current is fed to all the transistors in this current mirror circuit, and the effect of the channel length modulation onto the MOSFETs M1 and M3 is identical thereby enabling the input output current ratio to be decided with high accuracy.
Abstract: PURPOSE:To obtain a current output with high accuracy over a wide output voltage range with a high output resistance by making drain-source voltages of transistors (TRs) deciding a ratio of an input current to an output current equal to each other so as to eliminate the error due to the channel length modulation. CONSTITUTION:N-channel MOS TRs are all used and the relation between an input current Iin and an output current Iout is designed to be made identical. The ratio W/L of the channel width to the channel length of a MOSFETM 6 only is 1/4 in comparison with that of the other TRs. The same input current is fed to all the TRs in this current mirror circuit. Since the drain-source voltage of the MOSFETs M1, M3 deciding the ratio of the input current in to the output current Iout is both DELTAV, the effect of the channel length modulation onto the MOSFETs M1 and M3 is identical thereby enabling the input output current ratio to be decided with high accuracy.
TL;DR: In this paper, the reverse bias current of polysilicon p+in+ diode with an MOS gate was examined and it was found that the mechanism of this current is Poole-Frenkel current.
Abstract: The drain current in polycrystalline silicon (polysilicon) TFTs (Thin Film Transistors) increases with increase of the gate voltage even if the polarity of the gate voltage is opposite to that of the drain voltage. This behavior is different from that in single-crystal silicon MOSFET's. In this paper, to clarify the mechanism of this drain current, the dependence of the reverse bias current of polysilicon p+in+ diode with an MOS gate on voltage and temperature is examined. As a result, it is found that the mechanism of this current is Poole-Frenkel current. Moreover, a simple model to explain the voltage and temperature dependence of this drain current is proposed, and its propriety is shown.