Showing papers on "Channel length modulation published in 1989"

Physical models for amorphous-silicon thin-film transistors and their implementation in a circuit simulation program

Abstract: A semianalytic theory to describe both the current-voltage and capacitance-voltage characteristics of amorphous silicon thin-film transistors on the basis of their physics of operation is presented. In this model, the drain current is directly related to the electron concentration at the source side of the channel. This enables one to describe the various regimes of operation of these devices (i.e. subthreshold or above threshold) using only one equation. The output conductance of these devices in saturation is also considered, and it is shown that the finite output impedance is a consequence of the drain voltage modulating the effective channel length by creating a space-charge limited current region of variable length near the drain. The results of this model are in good agreement both with experimental data and the results of comprehensive two-dimensional simulations. These device models have been successfully incorporated into a SPICE circuit simulation program. >

Physical mechanisms for short channel effects in polysilicon thin films transistors

Abstract: It is demonstrated that channel avalanched multiplication is the dominant mechanism giving rise to short-channel threshold shifts in n- and p-channel polysilicon thin-film transistors (TFTs) at moderate or high drain bias The effects are greater in nMOS TFTs than pMOS due to the higher ionization rates for electrons in comparison to holes At low drain bias, a charge sharing mechanism dominates and p-channel devices show greater threshold shifts Device design parameters such as gate oxide or active island thickness have little influence, and the most effective method for reducing the threshold shifts is to reduce the supply voltage When the supply voltage is scaled to maintain a fixed minimum threshold voltage, CMOS circuit speeds decrease at shorter gate lengths when a fixed capacitive load is driven, although in more complex circuits the speed improves >

An empirical model for the L/sub eff/ dependence of hot-carrier lifetimes of n-channel MOSFETs

Abstract: An empirical model that describes the dependence of hot-carrier lifetime on the effective channel length of an n-channel MOSFET, allowing the estimation of the lifetimes of transistors of a given length based on data from a limited number of channel lengths, is presented. The model takes into account the localization of hot-carrier induced damage and shows that the size of the damaged region relative to the total length of the transistor is important in determining the effect of hot-carrier-damage-induced transistor characteristics. The results are integrated into two commonly used equations for hot-carrier lifetimes of MOSFETs of a given channel length under DC operation. The model is experimentally verified for MOSFETs of effective channel lengths between 0.45 and 2.7 mu m. >

Parameter extraction from I-V characteristics of single MOSFETs

Abstract: A method is presented to extract the bias-dependent series resistances and intrinsic conductance factor of individual MOS transistors from measured I-V characteristics. If applied to groups of scaled channel length devices, it also allows determination of the effective channel length together with the transversal field dependence of the carrier mobility. The method is exactly derived from conventional MOS theory based on the gradual channel approximation, and the deviations from such an ideal case are studied by means of two-dimensional device simulations. Experimental results obtained with n- and p-channel transistors of conventional as well as LDD type are presented to show the correctness of the proposed extraction procedure. >

Anomalous punchthrough in ULSI buried-channel MOSFETs

Abstract: It is shown that punchthrough (pt) in very short buried-channel P-MOSFETs cannot be suppressed by diminishing the p-channel thickness t/sub c/. This is because of the drain-induced channel enlargement (DICE) effect, which switches on and becomes the dominant pt mechanism for very short channels. The DICE effect is independent of t/sub c/, and therefore the DICE-related pt component flows even with t/sub c/ to 0, so that strategies other than channel thinning are needed for the pt to be suppressed. A new implant step, called the retrograde implant, together with the LDD (lightly doped drain) structure, is shown to be able to suppress the DICE effect and thereby shift the limit of pt-immune BC-P-MOSFETs from 0.6 mu m down to 0.3 mu m. The pt encountered below a channel length of 0.3 mu m has been found to result from a pure DIBL effect rather than an incomplete DICE effect suppression. As a result, a further gain in channel shortening (without pt) would require the channel to be even thinner than 0.04 mu m. >

Two stage protection circuit for a power MOSFET driving an inductive load

Abstract: A snubber circuit comprising two stages regulates the gate current of a MOSFET in relation to the drain voltage at turnoff to clamp transient inductive voltages to a nondestructive level. At the onset of the turnoff, a current source is activated to discharge the gate capacitance, and the snubber controls the magnitude of such current in relation to the sensed drain voltage to stabilize the drain voltage at a nondestructive level. When the drain voltage approaches its limit value, a current injection circuit supplies additional current to the gate to sustain the MOSFET conduction, again in relation to the sensed drain voltage. When the inductive energy stored in the load is substantially dissipated, the drain voltage falls; at such point, the current injection circuit is disabled and the conduction of the current source is increased to complete the turnoff of the MOSFET.

Striped channel field effect transistors with a modulation doped structure

Abstract: The authors report the fabrication and performance of the striped channel field effect transistor, which consists of a multiple number of narrow channels fabricated on a modulation-doped heterostructure The two-dimensional squeezing of the conducting channel by applying gate voltage has been confirmed from the channel width dependence of the drain current By reducing the channel width of the fabricated 025- mu m-gate-length striped channel devices, the authors have observed an enhancement in transconductance as well as improved high-frequency performances Furthermore, more-than-three-times improvement in the maximum transconductance has been obtained when the device is cooled to 77 K These results are interpreted based on the improved charge controllability due to the channel squeezing effect as well as on the excellent electron transport properties of ultrafine channels >

Current variation reduction for mosfet current sources

Abstract: A current variation reduction circuit for metal oxide semiconductor field effect transistors, which are controlled by the application of a drive voltage between the gate and drain terminals, includes a circuit for applying a compensation current to the gate terminal. The compensation current is of substantially equivalent magnitude and opposite polarity to current in the source to gate capacitance of the MOSFET in response to a change in the source to drain voltage of the MOSFET.

Negative resistance in the output characteristics of SOI MOSFETs

Abstract: Summary form only given. The output characteristics (I/sub DS/ vs. V/sub DS/) of thin-film SOI MOSFETs show a decrease in drain current for increasing drain-source voltage at high power densities. In addition, the pinch-off point is shifted for small channel length, an effect inconsistent with theory due to the suppression of the body effect in these transistors. In an investigation of these phenomena it was found that both the negative resistance and the movement of the pinch-off point arise from a degradation of mobility caused by local heating due to power dissipation in the channel. This is a result of the poor thermal conductivity of the buried oxide; a worst case is that of a thin-film transistor on a thick buried insulator. >

Generalized transconductance and transresistance methods for MOSFET characterization

Abstract: The concept of transconductance is generalized to include substrate and drain transconductances in addition to the usual gate transconductance. Generalized transresistances are defined as the ratio of transconductance to square of conductance, and their proportionality to channel length and reciprocal square of gate drive is exploited to develop six new analytical methods for determination of MOSFET threshold voltage and channel length. Quantitative expressions for the error components due to short channel geometry effects, asymmetry and bias dependence of source and drain series resistances, and mobility degradation are derived and related to total threshold voltage and channel length errors of various methods. In one set of methods the channel length error due to bias dependence of series resistance is eliminated by extrapolation to zero gate drive. Estimated errors agree well with measurements on submicron LDD transistors and the high precision of the gate transresistance technique is demonstrated with a channel length error of 3 nm limited by instrument resolution. Threshold voltage accuracy of 2 mV is obtained with the square-root substrate transresistance technique when series resistance is independent of substrate bias.

MOSFET for producing a constant voltage

Abstract: A circuit for producing a constant voltage comprises first and second MOSFETs, and first and second bias voltage producing devices. The first and second MOSFETs to which first and second input voltages are applied, respectively, are connected in series. The first bias voltage producing device produces a potential difference, which is equal to a threshold voltage of the first MOSFET, to be applied across drain and gate of the first MOSFET, and the second bias voltage producing device produces a potential difference, which is equal to a threshold voltage of the second MOSFET, to be applied across drain and gate of the second MOSFET, so that a wide range of an output voltage is produced at a connecting point of the first and second MOSFETs. Even more, the output voltage is stabilized in level, even if the threshold voltages fluctuate in a semiconductor device fabricating process.

Accuracy of the charge pumping technique for small geometry MOSFETs

Abstract: The channel-length dependence of the charge-pumping current for MOSFETs is investigated using a two-dimensional simulation technique. The dependence of charge-pumping current on signal offset voltage for various MOSFET channel lengths is studied using energy-dependent interface trap distributions. Simulation results are compared to experimental charge-pumping measurements on irradiated MOSFETs with different gate lengths with good agreement for the shape of the curves. It is found that as the effective channel length decreases the accepted charge pumping model has decreasing accuracy that results in an underestimation of the mean interface trap density. The loss in accuracy is due to the nonuniformity of surface potential across the channel caused by source/drain proximity. Using the charge-pumping technique to measure interface trap densities on advanced devices with an effective channel length less than 1 mu m may result in unacceptable errors. >

The extraction of electrical parameters for MOSFETs with applications to low temperature

Abstract: The authors examine six models for predicting triode region MOSFET behavior. The six models are formed from the combination of two channel charge models and three carrier velocity models. The channel charge and velocity descriptions are well documented in the literature, but only four of the models have been compared with experiment. It is shown that all six models predict identical MOSFET characteristics for sufficiently small drain voltages. It is shown that, at temperatures high enough that channel carrier freezeout is negligible, it is acceptable to extract MOSFET parameters from the transfer characteristics using methods derived from the simple square law model without velocity saturation. However, due to channel carrier freezeout onto the minority impurity sites for device bodies which contain both donors and acceptors, these methods are invalid at low temperatures. It is also shown that the hole saturation velocity in the channel increases with decreasing temperature. Between room and liquid-nitrogen temperatures, the increase is about 44%. >

An improved CMOS current mirror using a bulk-effect independent cascode biasing structure

Abstract: To reduce the channel length modulation effect, a cascode structure is very often used in current mirrors. However, this technique requires a correct biasing of the cascode transistor. The author presents a biasing structure which always guarantees the correct biasing under any process variations (parameter variations from chip to chip) or any bulk effect and ensures that all the transistors are always biased just in saturation. As a result a current mirror is realized which has a maximum voltage output swing and a very high current mirror accuracy. >

MOSFET interface state densities of different technologies

Abstract: In order to determine the relationship between channel length and interface state density, a test structure with sets of n-channel and p-channel transistors having different channel lengths was used. The transistors had the same width and were situated side by side. A transistor with a gate in a trench was also tested. Charge pumping measurements showed conventional nMOSFETs to have the lowest interface state density, followed by conventional pMOSFETs, LDD nMOSFETs, and trench channel transistors. No increase of interface state density was found for submicron MOSFETs in comparison with long-channel transistors. >

Contact resistance measurements of a MOSFET

Abstract: The author examines in detail a recent technique for measuring contact resistance of a MOSFET It is observed that the equations used for determining the contact resistance based on the 'diode' mode and the 'MOSFET' mode differ by a constant factor depending on the device geometry in the limit when the sheet resistance dominates Ideally, the ratio of the probe voltage/drain current (V/sub m//I) is independent of the drain current and always higher for the MOSFET mode In the measurement of a conventional MOSFET, a current-dependent V/sub m//I is observed This could be explained by the presence of a depletion region near the voltage probe A word of caution is given with regard to the effects of leakage in the oxide side-wall for a small-geometry MOSFET

A self‐consistent model for short‐channel mosfets

Abstract: A de model for short-channel MOSFETs is presented in this paper. Several second-order effects associated with small-geometry MOSFETs such as mobility degradation, carrier velocity saturation and channel length modulation are included in the model. The analysis emphasizes the modeling of the output conductance and the transconductance which are important in analogue circuit simulation. The theoretical predictions of the model are in good agreement with the experimental data available in the literature.

Substrate bias effects on short channel length and narrow channel width PMOS devices at cryogenic temperatures

Abstract: The effects of substrate biasing on the characteristics of PMOS devices with varying channel lengths and widths were studied as a function of temperature from 300 K to 77 K. Results on the low field intrinsic mobility, the mobility surface and substrate bias degradation constants, and the effective low field mobility are discussed. The variation of the peak substrate current normalized to the drain current and of drain-induced-barrier-lowering with substrate bias for both groups of devices is also presented and discussed. >

Level converter circuit with two MOSFET(s) - has drain electrode of third MOSFET coupled to drain-source path of second MOSFET

Abstract: The CMOS inverter consists of two MOSFETs (T1,2), in which the first MOSFET (T1) source electrode is coupled to a first operating voltage source (UEE). A third MOSFET (T3) drain electrode is coupled to the second MOSFET (T2) source drain path. The third MOSFET gate electrode is coupled to its drain electrode. The third MOSFET source electrode is connected to a second operating voltage source (USS). The second and third MOSFETs are of an identical channel type. Pref. the first MOSFET is of a p-channel type, with the third and second MOSFETs of an n-channel type. ADVANTAGE - TTL compatibility, and mfr. by standard CMOS process.

Hot-carrier degradation of LDD n-channel MOSFETs at 77 K

Abstract: Hot-carrier degradation in lightly-doped drain (LDD) n-channel MOSFETs stressed at 77 K and 300 K was studied. Both short (L=1.3 mu m) and long (L=50 mu m) channel devices were stressed with both DC and pulsed gate biases. Short channel devices were stressed with a drain voltage of 5 V. The DC gate bias was 2.4 V, and the pulsed gate signal was a 1 MHz square wave of 0 to 5 V. Long channel devices were stressed at a drain voltage of 6 V, with the gate pulsed from -7 to 15 V. Drain characteristics and charge-pumping measurements indicate interface state generation at the drain end of the channel. In addition, hole injection led to trapped holes in the oxide at the drain end of the channel. Electron trapping at trapped hole sites in the oxide was observed in the long channel devices. >

A quasi-two-dimensional model for small-geometry MOSFETs including the source/drain resistances

Abstract: A quasi-two-dimensional model (El Banna and El Nokali 1988) for small geometry MOSFETs has been modified to include the effects of source/drain series resistances. A simple method that guarantees the continuity of the output conductance at the onset of saturation is proposed. Several second order effects, such as mobility degradation due to surface roughness, carrier velocity saturation, and channel length modulation have been included to account for the two-dimensional nature of small-geometry MOSFETs. The accuracy of the model is confirmed by comparing its theoretical predictions with the experimental data available in the literature. The model is also used to estimate the lateral field to which hot-carrier effects are sensitive.

An analytical model for short-channel MOSFET capacitances

Abstract: An analytical model for the intrinsic capacitances in the strong inversion regime of short-channel MOS transistors is developed. The mode is based on the computation of the charges associated with the four terminals of the device. The model has followed the charge-based approach, which consists of defining charges rather than capacitances as the state variables, thus avoiding the charge nonconservation problem associated with J.E. Meyer's (1971) approach. Major second-order effects such as carrier velocity saturation, mobility degradation, and channel length modulation are included in the model. The theoretical predictions of the model are compared to the numerically simulated data resulting from CADDETH and are found to be in good agreement over a wide range of gate and drain voltages. >