Showing papers on "Channel length modulation published in 1991"

Insulated gate field-effect transistor with pulse-shaped doping

Abstract: A silicon MOSFET is provided, which can be made with an effective channel length of under one micrometer without incurring severe short-channel effects. The MOSFET includes first and second channel regions located between the source and drain regions, the first channel region overlaying the second channel region. The second channel region has a higher carrier density than the first channel region, and functions as a buried ground plane.

Physics and technology of ultra short channel MOSFET devices

Abstract: It is pointed out that, as MOSFET channel lengths are scaled below about 0.15 mu m, nonstationary carrier transport effects become increasingly important. These effects can result in increased drain current over what is expected from stationary transport theory (i.e. velocity saturation), and in decreased hot-carrier energy spectrum spread, or carrier temperature, leading to improved device reliability. However, the magnitude of these effects depends strongly not only on channel length but also on overall device design such as channel doping configuration, drain junction depth, etc. Besides minimization of junction depths, optimal device design requires a super-steep-retrograde channel doping, with surface doping concentration no higher than mid-10/sup 16/ cm/sup -3/. This can be achieved with indium doping for NMOS, and antimony or arsenic doping for PMOS extreme submicron transistors. >

New short-channel n-MOSFET current-voltage model in strong inversion and unified parameter extraction method

Abstract: A semiempirical strong inversion current-voltage (I-V) model for submicrometer n-channel MOSFETs which is suitable for circuit simulation and rapid process characterization is proposed. The model is based on a more accurate velocity-field relationship in the linear region and finite drain conductance due to the channel length modulation effect in the saturation region. The parameter extraction starts from the experimental determination of the MOSFET saturation current and saturation voltage by differentiating the output characteristics in a unified and unambiguous way. These results are used in order to systematically extract the device and process parameters such as the effective electron saturation velocity and mobility, drain and source series resistances, effective gate length and characteristic length for channel length modulation, and short-channel effects. The values agree well with other independent measurements. The results of experimental studies of wide n-MOSFETs with nominal gate length of 0.8, 1.0, and 1.2 mu m fabricated by an n-well CMOS process are reported. The calculated I-V characteristics using the extracted parameters show excellent agreement with the measurement results. >

Method and apparatus for high power pulse modulation

Abstract: A method and apparatus for high power pulse modulation which includes a high voltage supply to provide a high voltage input signal, and a drive channel, rise channel, fall channel, and dump channel. A timing system controls the switching of the drive channel, rise channel, fall channel, and dump channel to modulate the high voltage input signal to produce an output signal. Each channel comprises a channel logic input, buffer amplifier, alternating current (AC) coupler, isolation pulse transformer, current limiter, and switch to provide the pulse modulation. Power MOSFETs can be used as switches in the four channels.

Graded-junction gate/n/sup -/ overlapped LDD MOSFET structures for high hot-carrier reliability

Abstract: A newly developed gate/n/sup -/ overlapped LDD MOSFET was investigated. The MOSFET was fabricated by an oblique rotating ion implantation technique. A formula for the impurity ion profile was derived to analyze the lowering of substrate current and improvement of the degradation caused by the hot-carrier effect of the MOSFET. It was proved that the impurity ion profile near the drain edge is remarkably graded in the directions along channel and toward substrate even just after the implantation, so that the maximum lateral electric field is relaxed as compared with conventional LDD MOSFETs. Also, the maximum point of the lateral electric field at the drain edge is located apart from the main path of the channel current. >

A new three-dimensional MOSFET gate-induced drain leakage effect in narrow deep submicron devices

Abstract: A new MOSFET gate-induced drain leakage (GIDL) mechanism is observed in narrow-width trench-isolated MOSFET devices Electrical measurements and device simulation show that this mechanism occurs due to electric-field enhancement at the three-dimensional intersection of the gate-to-drain overlap region and the trench corner The enhanced electric field increases the GIDL current at the 3-D intersection region This imposes another fundamental limit on MOSFET dielectric scaling in deep submicron narrow-width devices Since the 3-D GIDL mechanism is caused by a high electric field, trench corner rounding and lightly doped drain junctions provide effective solutions >

Semiconductor device having at least two field effect transistors and method of manufacturing the same

Abstract: A complementary field effect transistor with an N channel MOSFET and a P channel MOSFET formed on the same substrate is disclosed. On the P type main surface of the semiconductor substrate, an N channel MOSFET is formed comprising a gate electrode and a pair of impurity regions which becomes a pair of source/drain regions. Each impurity region of the N channel MOSFET comprises an impurity region of relatively low concentration formed so as to extend to beneath the above mentioned gate electrode, and an impurity region having a concentration higher than that of said impurity region having low concentration formed in a position at a distance from said gate electrode joining the impurity region of low concentration. The length of the portion located beneath the above mentioned gate electrode in the surface portion of the impurity region of low concentration is not less than 0.1 μm in the direction identical to the direction of the channel length. This complementary field effect transistor has both reliability and high speed in the N channel MOSFET, and without punch-through in the P channel MOSFET, even though the devices become more minute.

A submicrometer MOS transistor I-V model for circuit simulation

Abstract: A MOSFET I-V model (MOSTSM) that is composed of simple analytical equations applicable down to a 0.5- mu m MOSFET operation is proposed. This model provides enhanced performance with respect to gate electric field effects on channel conductance and channel-length modulation in saturation operation. Subthreshold conduction is modeled, and simple and accurate geometrical effect (channel length; L) formulations for the model equations are developed. Features of the model are channel-length dependency of threshold voltage and effective channel conductance. A formulation of body factor on device threshold (K/sub b/) is proposed as a function of channel length. Experiments were conducted using various devices to demonstrate the model accuracy. The experimental results show that the MOSTSM model ensures curve-fitting accuracy within 1% for maximum average error over biases, even when the geometry effects are included. The devices used in the experiments were in the 0.5-2.0- mu m range of CMOS fabrication technology. >

An improved analytical LDD-MOSFET model for digital and analog circuit simulation for all channel lengths down to deep-submicron

Abstract: An improved analytical LDD (lightly doped drain)-MOSFET model for digital and analog circuit simulation in the deep-submicron region is described This model includes all short and narrow channel effects and a substrate current model Special emphasis was placed on the voltage-dependent effective channel length and series resistance of LDD devices The voltage-dependent channel length and series resistance of LDD devices are measured electrically, verified with capacitance measurements, and introduced into the model >

MOS field effect transistor having source/drain regions surrounded by impurity wells

Abstract: Disclosed is a MOSFET for controlling the flow of a large number of carriers from one source/drain region to the other source/drain region by applying a voltage to a gate. This MOSFET includes a semiconductor substrate and a transistor. The transistor includes a gate provided on the semiconductor substrate, one source/drain region and the other source/drain region both having a first conductivity type. The MOSFET includes first and second wells of a second conductivity type formed apart from each other on opposite sides of the gate in the main surface of the semiconductor substrate. The first well is such a small well as to accommodate only one source/drain region, while the second well is such a small well as to accommodate only the other source/drain region. The one source/drain region and the other source region are formed in the first and second wells, respectively. No distortion due to thermal stresses remains in the resultant MOSFET, and consequently a highly reliable MOSFET is obtained.

New simulation methods for MOS VLSI timing and reliability

Abstract: A novel approach to incorporating the channel length modulation in a direct-equation solving fast timing simulator is presented along with a mixed event-driven and waveform relaxation algorithm to handle MOS VLSI circuits with feedback. Simulation speedup of 3N over SPICE-like simulators has been observed, where N is the number of transistors. The simulator is able to simulate circuits as large as 235000 transistors in 10 min real time. Also presented is a novel approach to fast hot-carrier reliability simulation. These methods make it possible to achieve accurate and fast hot-carrier reliability simulation of MOS circuits each with as many as hundreds of thousands of MOS transistors in a workstation environment. >

Physical mechanism of the “reverse short-channel effect” in MOS transistors

Abstract: The threshold voltage of short-channel-length MOS transistors may increase as the channel length of the device is decreased. This phenomenon is due to the existence of a potential barrier at the edge of the channel to the source/drain junction. This model was demonstrated experimentally with the drain current and the transconductance vs gate-voltage characteristics of short-channel length MOS transistors. It is shown that a potential barrier can strongly degrade the performance of MOS transistors.

New Short-Channel n-MOSFET Current-Voltage Model in Strong Inversion and Unified Parameter Extraction Method Byung-Jong Moon, Student Member, IEEE, Chan-Kwang Park, Student Member, IEEE,

Abstract: We propose a new semi-empirical strong inversion cur- rent-voltage (I-V) model for submicrometer n-channel MOSFET's which is suitable for circuit simulation and rapid process character- ization. Our model is based on a more accurate velocity-field relation- ship in the linear region and finite drain conductance due to channel length modulation effect in the saturation region. Our parameter ex- traction starts from the experimental determination of the MOSFET saturation current and saturation voltage by differentiating the output characteristics in a unified and unambiguous way. We use these results in order to extract the device and process parameters such as the effective electron saturation velocity and mobility, drain and source series resistances, effective gate length and characteristic length for channel length modulation, and short-channel effects systematically. The deduced values agree well with other independent measurements. We report the results of experimental studies of wide n-MOSFET's with nominal gate lengths of 0.8, 1.0, and 1.2 pm fabricated by n-well CMOS process. The calculated I-V characteristics using the extracted parameters show excellent agreement with the measurement results. The salient feature of our approach is that it allows the automatic pa- rameter extraction in a systematic and unified manner, which is ex- tremely versatile for statistical yield analysis due to parameter varia- tion.

N-channel MOSFET model for the 60-300-K temperature range

Abstract: An engineering model of the short-channel NMOS transistor which is applicable to both room-temperature and cryogenic device operation is presented. The model incorporates the nonuniversal dependence of the effective channel mobility on the effective vertical field, which is ignored in room-temperature device models. Described also is a novel method to account for the bulk charge effect in the presence of drift velocity saturation, channel length modulation, charge sharing by the drain and source, and temperature dependence of the critical field. The proposed model is verified by comparison with experimental device characteristics obtained over a wide range of terminal voltages, temperatures, and channel lengths. >

Short channel effect in thin-film accumulation-mode p-channel SOI MOSFETs

Abstract: A short channel effect in thin-film accumulation-mode p-channel SOI MOSFETs is investigated. It is observed that a significant leakage current can flow in a short-channel p/sup +/pp/sup +/-device when it is turned off. Two dimensional numerical simulations reveal that the nature of this current in short-channel SOI MOSFETs is due to the combination of potential barrier lowering effects caused by the presence of a negative back-gate bias and that of a large drain voltage. >

A DC model for the HEMT including the effect of parasitic conduction

Abstract: A DC model for AlGaAs-GaAs high electron mobility transistor (HEMT) is proposed. The model considers the parasitic parallel conduction in AlGaAs, which becomes important for large gate voltages, together with other important effects, such as field-dependent mobility, channel length modulation, maximum concentration of the two-dimensional electron gas, and series resistances. The theoretical predictions of the model are compared with the experimental data and are found to be in good agreement over a wide range of bias conditions. >

A comparison of statistical variation of threshold voltage in bulk silicon and SOI MOSFETs

Abstract: Using previously developed models for the bulk and SOI (silicon-on-insulator) MOSFETs, the authors compare and analyze the statistical variation of the threshold voltage V/sub th/ in these MOSFETs with respect to variation of device parameters such as doping density, oxide thickness, and channel length. The statistical variation of the threshold voltage reduction Delta V/sub th/ for three values of channel length is shown. The statistical distribution is broadened with a pronounced asymmetry toward the higher value of Delta V/sub th/. It is also noted that the statistical distribution in the SOI MOSFET is narrower than that of the bulk MOSFET. The optimized design region of a fully depleted SOI MOSFET with a threshold voltage distribution smaller than its bulk silicon counterpart is shown. >

Field effect transistor having saturated drain current characteristic

Abstract: A field effect transistor has the property that the product of its series resistance and its true transconductance is less than one throughout the entire range of drain voltage in the operative state of the transistor, the series resistance being the sum of the resistance from source to channel and the resistance of this channel. In order to prevent an excessive increase in the active resistance of the channel, the channel is made to have an impurity concentration as low as less than 10 15 atoms/cm 3 , preferably less than 10 14 atoms/cm 3 , so that the depletion layers extending from the gates grow extensively to become contiguous in response to a small increase in the reverse gate voltage applied. As a result, the field effect transistor of this invention has an unsaturated drain current versus drain voltage characteristic.

Effect of lateral-field distribution on hot-carrier analysis in short-channel MOSFETs

Abstract: A previously developed quasi-two-dimensional model is used to examine the effect of the lateral-field distribution in the drain region on the different components of current in short-channel MOSFETs. Uniform, linear, and parabolic distributions are included in the model for the first time. Hot-carrier currents are found to be consistent with the experimental data available in the literature when a linear field distribution is assumed. The gate current is shown to be more sensitive than the substrate current to the selection of the field distribution. The more nonlinear the field distribution is, the longer the minimum channel length for reliable MOSFETs will be. Devices less than 0.5 mu m in channel-length are insensitive to the field distribution. >