Showing papers on "Channel length modulation published in 1992"

A new 'shift and ratio' method for MOSFET channel-length extraction

Abstract: A shift-and-ratio method for extracting MOSFET channel length is presented. In this method, channel mobility can be any function of gate voltage, and high source-drain resistance does not affect extraction results. It is shown to yield more accurate and consistent channel lengths for deep-submicrometer CMOS devices at room and low temperatures. It is also found that, for both nFET and pFET, the source-drain resistance is essentially independent of temperature from 300 to 77 K. >

Unified MOSFET model

Abstract: We present a basic analytical MOSFET model which describes both the below and above threshold regimes of device operation. The description is based on a charge control model which uses one unified expression for the effective differential channel capacitance. The model also accounts for series drain and source resistances, velocity saturation in the channel, finite output conductance in the saturation regime, and for the threshold voltage shift due to drain bias induced lowering of the injection barrier between the source and the channel (DIBL). The model parameters, such as the effective channel mobility, the saturation velocity, the source and drain resistances, etc. are extractable from experimental data. The model has been incorporated into our simulator, AIM-Spice. We apply the characterization procedure based on this model to a MOSFET with a quarter micron gate length and obtain excellent agreement with experimental data.

Modeling of amorphous-silicon thin-film transistors for circuit simulations with SPICE

Abstract: A static and dynamic model for amorphous silicon thin-film transistors is presented. The theory is based on an assumed exponential distribution of the deep states and the tail states in the energy gap. Expressions are derived that link the density of the localized states and the temperature to the drain current and the distribution of the charge in the transistor channel. In addition the authors take into account parasitic effects such as channel length modulation, off-resistance, drain and source resistances, mobile and free charges in the insulator, surface states, and overlap capacitances. The model is incorporated into the circuit simulation program SPICE. Charge conservation problems are overcome by using a charge-oriented dynamic transistor model. Simulated and measured current-voltage characteristics agree well. A 96-b gate line driver for addressing liquid-crystal displays, which was successfully designed and optimized with the model, is introduced. >

A CMOS square-law programmable floating resistor independent of the threshold voltage

Abstract: A CMOS architecture for a floating linear resistor which exploits the square-law model of the MOS transistor is presented The architecture is programmable by DC control voltage and is easily modified such that it is threshold-voltage independent, allowing large signal handling and immunity to substrate noise Design trade-offs and device size optimization are investigated Second-order effects due to mobility degradation and channel length modulation are analyzed and a simple high frequency model for the resistor is developed The architecture is fabricated in a 2 mu m p-well CMOS MOSIS process The resistor occupies 210 mu m*270 mu m, consumes 04-40 mW with +or-5 V supply and exhibits a signal (at 1% THD) to noise ratio of more than 100 dB over a 1 V range of the DC control voltage >

Source-to-drain nonuniformly doped channel (NUDC) MOSFET structures for high current drivability and threshold voltage controllability

Abstract: The source-to-drain nonuniformly doped channel (NUDC) MOSFET has been investigated to improve the aggravation of the V/sub th/ lowering characteristics and to prevent the degradation of the current drivability. The basic concept is to change the impurity ions to control the threshold voltage, which are doped uniformly along the channel in the conventional channel MOSFET, to a nonuniform profile of concentration. The MOSFET was fabricated by using the oblique rotating ion implantation technique. As a result, the V/sub th/ lowering at 0.4- mu m gate length of the NUDC MOSFET is drastically suppressed both in the linear region and in the saturation region as compared with that of the conventional channel MOSFET. Also, the maximum carrier mobility at 0.4- mu m gate length is improved by about 20.0%. Furthermore, the drain current is increased by about 20.0% at 0.4- mu m gate length. >

A new type of tunnel-effect transistor employing internal field emission of schottky barrier junction

Abstract: A new type of tunnel-effect transistor, which has nearly the same structure as conventional metal-oxide-silicon field-effect transistors (MOSFET's) except for a Schottky barrier source contact and a low resistivity channel layer, has been proposed. The structure has the advantage of an easy fabrication process and is capable of submicron channel length without the short channel effect. In the proposed device the drain current is controlled by the gate bias through the tunnel injection of electrons at the Schottky barrier source contact. A 2-D device simulation has shown that this device can have a high transconductance of 138 mS/mm at a drain voltage of 2 V.

Inverted thin-film transistors with a simple self-aligned lightly doped drain structure

Abstract: The I-V characteristics of inverted thin-film transistors (TFT) are studied. A simple lightly doped drain (LDD) structure is utilized to control the channel electric field at the drain junction and to improve the performance of the TFTs. The LDD region is self-aligned to the channel and the source/drain regions. It is created by a spacer around an oxide mask which exclusively defines the channel length L/sub ch/. Experimental data show that the leakage current, subthreshold swing SS, saturation current, and on/off current ratio of the inverted TFTs are closed related to L/sub ch/, L/sub LDD/, the drain bias, gate voltage, and LDD dose. With a gate deposited at low temperature, a saturation current of approximately 1.25 mu A at 5 V and a leakage current of approximately 0.03 pA per micrometer of channel width were achieved. The current ratio therefore exceeds seven orders of magnitude, with an SS of 380 mV/decade. At 3.3 V, the current ratio is approximately 7*10/sup 6/. >

Modeling the anomalous threshold voltage behavior of submicrometer MOSFET's

Abstract: A simple yet accurate semi-empirical analytical model for simulating the anomalous threshold voltage behavior in submicrometer MOSFETs is reported. The increase in the threshold voltage with decreasing channel length has been modeled by assuming a bias-independent, but channel-length-dependent, fixed charge at the source and drain ends. The new model requires two extra parameters in addition to the usual short-channel threshold voltage model parameters. These two parameters represent the magnitude of the fixed charge and the length over which the charge is spread at the source and drain ends. The model shows excellent agreement with the experimental threshold voltage data (within 2%) for submicrometer devices with varying oxide thickness, junction depth, and channel doping concentration. >

Low impedance, high voltage protection circuit

Abstract: A low impedance overvoltage protection circuit includes a first MOSFET having a drain connected to an input signal and a source connected to a drain of a second MOSFET, the source of the second MOSFET being coupled to the output The gates of the first and second MOSFETs are connected to voltage supplies which float relative to the input signal values so as to maintain the gates of the respective MOSFETs biased to a conducting state The maximum and minimum values to which the floating voltage supplies will float are defined by clamping diodes and clamp voltage sources When the input signal value exceeds a desired positive maximum value, the first MOSFET is no longer biased to an on state whereby the MOSFET turns off, shunting the input signal through a high impedance for limiting input current and removing the input signal from the output Negative going peak values are removed in a like manner by the second MOSFET Bipolar transistors are coupled to each MOSFET to allow quick turn off in the event of rapid rise time transient input values

CMOS device with perpendicular channel current directions

Abstract: P channel MOSFET and N channel MOSFET are formed in a (011) orientated semiconductor surface in such a manner that the channel of the P channel MOSFET is perpendicular to the channel of the N channel MOSFET. This arrangement can reduce a total channel resistance. The P channel MOSFET is formed so that the channel is parallel to the direction, for example, and the N channel MOSFET is formed so that the channel is perpendicular to the direction.

Simulation and modeling

Abstract: A method for removing the discontinuity in G/sub ds/ going from the linear region to the saturation region in the MOS level 3 model of SPICE by modifying the channel length modulation expression is described. A detailed analysis of the problem and simulation results before and after the modification are presented. >

p-MOSFET total dose dosimeter

Abstract: A p-MOSFET total dose dosimeter where the gate voltage is proportional to the incident radiation dose. It is configured in an n-WELL of a p-BODY substrate. It is operated in the saturation region which is ensured by connecting the gate to the drain. The n-well is connected to zero bias. Current flow from source to drain, rather than from peripheral leakage, is ensured by configuring the device as an edgeless MOSFET where the source completely surrounds the drain. The drain junction is the only junction not connected to zero bias. The MOSFET is connected as part of the feedback loop of an operational amplifier. The operational amplifier holds the drain current fixed at a level which minimizes temperature dependence and also fixes the drain voltage. The sensitivity to radiation is made maximum by operating the MOSFET in the OFF state during radiation soak.

Accurate MOS threshold voltage detector for bias circuitry

Abstract: A circuit for the detection of the threshold voltage V/sub TH/ of MOS devices is presented. The basic scheme proposed here is implemented in BiCMOS technology but can also be applied in any standard CMOS process. The deviation of the detected V/sub TH/ from the actual (or extrapolated) one is analytically estimated, taking into account the effects due to channel length modulation and mobility modulation. The results obtained show that the error at ambient temperature is lower than 0.6% for all values of V/sub DD/ larger than 3.25 V, and for temperatures in the range -25 degrees C to 125 degrees C the error is never higher than 4%. >

Field effect transistor with offset region

Abstract: In a high breakdown voltage MOSFET having an offset region consisting of a low concentration impurity layer with the same conductivity type as that of a drain region between a channel region and the drain region, an impurity layer with conductivity type opposite to that of the drain region is formed on the surface of the offset region. With such a constitution, even for the case when the energy levels generated in the interface of silicon/oxide film under the environment of exposure to radiations act as the scattering centers, the drain current will not be affected by the levels. Further, the reliability of the high breakdown voltage MOSFET can be improved markedly, by suppressing the deterioration in the charge mobility due to generation of the interface levels and the accompanying reduction in the drain current.

CMOS full-wave operational transconductance rectifier with improved DC transfer characteristic

Abstract: The proposed full-wave rectifier is based on a source-coupled pair associated with a new current-mode circuit that computes the absolute value of the difference of two currents. The DC transfer characteristic is well controlled through technology parameters because device mismatches and channel length modulation give rise to distinct imperfections. In addition, it reaches zero output current at the origin in every case. These properties make the circuit suitable for dense implementation of Manhattan distance computation in analogue VLSI neural networks.

Channel-length-independent hot-carrier degradation in analog p-MOS operation

Abstract: The hot-carrier degradation of p-MOSFETs in analog operation is investigated. In accordance with analog operation requirements, the damage is characterized by the drain conductance and the data are taken from devices with channel lengths between 1 and 10 mu m. In the important saturation range, a strong channel-length-independent degradation of the drain conductance is found. This result is explained by a simple analytic model. Other parameters such as the drain current or the transconductance show the usual channel length dependence. These results show that an increase in channel length does not generally solve problems related with hot-carrier degradation. Furthermore, the common digital hot-carrier constraints are shown to be insufficient to cover analog applications. >

Thin film transistor with reduced leakage current

Abstract: A thin film transistor (TFT) capable of reducing the leakage current on the occasion when the transistor is OFF and lowering the resistance of an interconnection layer connected to source/drain regions and a method of manufacturing the same are disclosed. In the thin film transistor, the length in the channel width direction of a polycrystalline silicon film 15 in junction parts 15c of a pair of source/drain regions 15b and a channel region 15a is smaller than the length in the channel width direction of polycrystalline silicon film 15 in source/drain regions 15b. Accordingly, the leakage current generated in junction parts 15c on the occasion when the TFT is OFF is reduced. In addition, it is unnecessary to reduce the length in the channel width direction of source/drain regions 15b, so that the resistance of an interconnection layer connected to source/drain regions 15b is lowered as compared to the conventional one.

Computationally efficient methods for accurate timing and reliability simulation of ultra-large MOS circuits

Abstract: A new approach to MOS circuit fast timing simulation is shown in this thesis. A generic MOS circuit primitive is shown along with the exact analytic solution of its state equation, a nonlinear Ricatti equation. A fast timing digital CMOS circuit simulator ILLIADS has been developed using the generic circuit primitive as well as its exact analytic solution. ILLIADS has been shown to be superior to other fast MOS timing simulators tested in both accuracy and speed. A modified waveform relaxation method for handling circuits with feedbacks is also presented in this thesis. A new algorithm taking advantages of event-driven technique and waveform relaxation method has been developed and applied. With this algorithm, simulation of a collection of ISCAS89 benchmark circuits reveals that the speedup of ILLIADS over SPICE is roughly 3N, where N is the number of transistors in a circuit. To incorporate the channel length modulation effect, an accurate and efficient method has also been developed. With this method, channel length modulation is handled with only a 10% speedup penalty. ILLIADS has been able to simulate a combinational circuit consisting of 235,000 transistors for one cycle output in 10.5 minutes real time in a workstation environment. Also presented in the thesis is a new first-time approach to fast circuit reliability simulation using a simple damaged transistor model. The new approach has made possible accurate and fast reliability simulation of large MOS circuits.

Analysis of Effective Channel Length in Amorphous Silicon Thin-Film Transistors

Abstract: This paper analyzes the effective channel length in amorphous silicon thin-film transistors (a-Si TFTs) by examining the parasitic channel length, ΔL, which causes the apparent dependence of the field-effect mobility of TFTs on the nominal channel length. The parasitic channel length is found to depend on the a-Si thickness, La, at the source path and the drain path of TFTs if there is no etching stopper insulator on the a-Si layer. An analytical formula for the parasitic channel length is derived by assuming that the space-charge-limited current is the dominant conduction mechanism through these paths. The validity of the analysis is confirmed by applying the formula to the experimental results on the ΔL-La relationship for a range of La between 0.18 and 0.98 µm.

Simple analytical model for short-channel MOS devices

Abstract: A simple analytical model derived from a quasi-two-dimensional analysis with a nonvanishing E-field derivative at the pinchoff point and a continuous output conductance at the transition point for short-channel MOSFETs is presented. This model also covers mobility reduction, carrier velocity saturation, body, channel-length modulation, source-drain series resistance and short-channel effects for an accurate determination of the pinchoff point location without internal numerical iterations as compared to other models. This model can be used to describe the channel-length modulation effects more accurately in circuit simulation with short-channel MOSFETs.

Metal‐oxide‐semiconductor field‐effect transistor characteristics as influenced by carrier mobility variation along the channel

Abstract: The electrical characteristics of metal‐oxide‐semiconductor field‐effect transistors (MOSFETs) are calculated within the gradual channel approximation by taking into account that the carrier mobility varies with position along the channel from source to drain due to the variation of electric field in the channel normal to the gate and by considering velocity saturation effects. It is found that for a typical buried channel p‐channel MOSFET the increased low‐field mobility with position from source to drain more than offsets the decreased mobility due to carrier saturation effects. For short‐channel devices saturation effects predominate.

Reverse Short-Channel Effects due to the Lateral Diffusion of the Point-Defects Induced by the Source/Drain Ion Implantation

Abstract: A physical model of reverse short-channel effect on the threshold voltage caused by the lateral diffusion of the Frenkel pairs (interstitial-vacancy) induced by tlie ion implantation in the source/drain region is presented Based on the process and device simulation, it is shown that the lateral diffusion of the Frenkel pairs enhances the diffusion of the channel dopant, which results in the nonuniform lateral distribution of the channel dopant and in the increase in the threshold voltage as the channel length is reduced

Modelling the channel-length modulation coefficient for junction field-effect transistors

Abstract: The saturation current-voltage characteristics of a junction field-effect transistor (JFET) are influenced by the effective conducting channel length of the device. The effective channel length is modulated by the gate voltage and the drain voltage due to the variation of the thicknesses of the depletion layers associated with the top-and bottom-gate of the JFET. For a given gate voltage, the effective channel length will shrink if the drain voltage is increased, a mechanism normally described by the channel-length modulation coefficient k. This paper develops a model for calculating λ, when combined with a recently developed JFET static model, this λ model can be used to predict the saturation behaviour of JFETs. Experimental data are included in support of the model.

Mosfet switch circuit

Abstract: PURPOSE: To protect the over current destruction of an output MOS field effect transistor(FET). CONSTITUTION: A drain point voltage VD1 of an output MOSFET Q1 is compared with a drain point voltage VD2 of a reference MOSFET Q2 by a comparator 2 and in the case of VD1>VD2, a gate voltage VG is dropped by operating a gate bias voltage limit circuit 14 provided with an NPN transistor N for protection use and forward in-series diode SD corresponding to a compared output voltage V2 of the comparator 2. Thus, the destruction of the transistor is prevented by always limiting the abnormal over current of a load current IL even at the switching transient time of the output MOSFET Q1. COPYRIGHT: (C)1994,JPO&Japio

Measuring the drain voltage dependent series resistance in submicron LDD MOSFET's

Abstract: Though already much attention was paid to the gate-voltage dependence of the MOSFET series resistance [1] the behaviour of the drain series resistance as a function of drain bias could not be measured until now. In this paper a general measurement principle to determine the series resistance in a LDD MOSFET as a function of drain bias is developed. Measured results for a 0.7 ?m device are given.

Analytical delay model of CMOS inverter including channel-length modulation

Abstract: An analytical delay model of a CMOS inverter is introduced for the first time which includes channel-length modulation, source-drain resistance and high-field effects. Calculations of the rise, fall and delay times show good agreement with SPICE simulations.

Numerical analysis of silicon-on-insulator short channel effects in a radiation environment

Abstract: Radiation-induced charge build-up in the buried oxide (BOX) of SOI MOSFETs affects device performance through threshold voltage shifts of the back channel. This charge build-up is related to the electric field in the BOX during irradiation. In this paper, we report on the application of a numerical model for the potential distribution in a semiconductor device to the task of determining the electric field in the BOX. This electric field distribution is then combined with a model for charge accumulation as a function of electric field during irradiation to predict the threshold voltage shifts in the back channel of SOI MOSFET devices as a function of channel length. For the device design analyzed here, this model agrees with available experimental data and predicts an increase in back channel threshold shift as the channel length enters the sub-micron regime.

Voltage drive semiconductor device

Abstract: PURPOSE: To obtain a voltage drive semiconductor device exhibiting ON resistance reducing effect through conductivity modulation just like an IGBT or a MOS thyristor in which voltage drop across junction is substantially eliminated while reducing power loss. CONSTITUTION: An n-source 1, a p-well 2, an n-drain 3 and a MOS gate electrode 10 constitute a MOSFET whereas the n-source 1, the p-well 2, the n-drain 3, an n-emitter 4, a p-base 5, and an n-collector 6 constitute a bipolar transistor. These transistors are integrated through the n-drain 3 and the n-emitter 4 of the same conductivity type. Holes are injected from the bipolar transistor having extremely low collector saturation resistance into the drain of the voltage drive MOSFET to cause conductivity modulation at the drain of the MOSFET thus reducing power loss of voltage drive semiconductor device significantly. COPYRIGHT: (C)1994,JPO&Japio

Analytical d.c. and small-signal a.c. modeling of Si delta(δ)-doped field effect transistors

Abstract: A model describing the d.c. and small-signal a.c. characteristics of Si delta(δ)-doped FETs is proposed. A quadratic expression of the charge control process is used and the model includes the effects of a field-dependent mobility and channel length modulation in the saturation region. The performance of Si δ-FETs is predicted from the model. The influence of some important design parameters is analyzed. An important result is that the effect of the charge control nonlinearity cannot be neglected in the analysis of δ-doped FETs.

MOS field-effect transistor

Abstract: A silicon MOSFET is provided, which can be made with an effective channel length of under one micrometer without incurring severe short-channel effects. The MOSFET includes first and second channel regions located between the source and drain regions, the first channel region 100 overlying the second channel region 90. The second channel region has a higher carrier density than the first channel region, and functions as a buried ground plane.