Showing papers on "Channel length modulation published in 1993"

Threshold voltage model for deep-submicrometer MOSFETs

Abstract: The threshold voltage, V/sub th/, of lightly doped drain (LDD) and non-LDD MOSFETs with effective channel lengths down to the deep-submicrometer range has been investigated. Experimental data show that in the very-short-channel-length range, the previously reported exponential dependence on channel length and the linear dependence on drain voltage no longer hold true. A simple quasi-two-dimensional model is used, taking into account the effects of gate oxide thickness, source/drain junction depth, and channel doping, to describe the accelerated V/sub th/ on channel length due to their lower drain-substrate junction built-in potentials. LDD devices also show less V/sub th/ dependence on drain voltage because the LDD region reduces the effective drain voltage. Based on consideration of the short-channel effects, the minimum acceptable length is determined. >

Three-dimensional "atomistic" simulation of discrete random dopant distribution effects in sub-0.1 /spl mu/m MOSFET's

Abstract: In this paper, discrete random dopant distribution effects in sub-0.1 /spl mu/m MOSFET's were studied using three-dimensional drift-diffusion "atomistic" simulations. Effects due to the random fluctuation of the number of dopants in the MOSFET channel and the microscopic random distribution of dopant atoms in the MOSFET channel were investigated. We found that, in addition to the well-known fluctuation of the threshold voltage, there was an average shift of the threshold voltage to a lower value. The average shift was believed to be attributed to the inhomogeneity of channel potential due to the discreteness of channel dopants, and the logarithmic dependence of subthreshold current. Microscopic dopant distribution also gave rise to asymmetry in drain current upon interchanging the source and the drain. >

Voltage-driven type semiconductor device

Abstract: According to the present invention, a MOSFET is formed of an n source, a p well, an n drain and a MOS gate electrode, a bipolar transistor is formed of an n emitter, a p base and an n collector formed in sequential order adjacent to the n drain. These transistors are formed by being merged with each other by the contact of n drain and the n emitter of the same conductivity type. Holes are injected into the drain of a voltage-driven type transistor comprised of the MOSFET from the bipolar transistor having a very small collector saturation resistance. With this, it is possible to give rise to conductivity modulation in the drain of the MOSFET, while the power dissipation of the voltage-driven type semiconductor device becomes very small.

Method for reducing on resistance and improving current characteristics of a MOSFET

Abstract: Construction and operation method for lightly doped drain MOSFET that has low or minimum drift on-state resistance and maintains high voltage blocking in the off-state. Temperature sensitivity of the electrical properties of the MOSFET are also reduced relative to MOSFETs produced by processes such as SIPOS. Voltage level shifting of p-channel and n-channel MOSFETs, produced according to the invention, relative to another voltage level is easily accomplished.

Threshold voltage controlled 0.1-/spl mu/m MOSFET utilizing inversion layer as extreme shallow source/drain

Abstract: MOSFETs containing sub-gates as sidewall spacers of the main gate are fabricated. The inversion layers induced in these MOSFETs by the sub-gates are used as source and drain, in order to investigate how the extremely shallow junction affects the short channel characteristics of MOSFETs. Significant improvement in the short channel characteristics is observed in comparison with conventional MOSFETs whose junctions are formed by ion implantation. These new MOSFETs do not show threshold voltage roll-off at the defined gate length around 0.1 /spl mu/m, and punchthrough is not observed down to 0.07 /spl mu/m. >

Thin film transistor with a sub-gate structure and a drain offset region

Abstract: A novel structure of a polycrystalline silicon thin film transistor manifested in a drain offset region and a sub-gate structure. The drain offset region is formed between a channel region and a drain region in the polycrystalline silicon thin film. The sub-gate structure comprises at least one sub-gate, except for a main gate which is provided in a normal field effect transistor. This structure is applicable to either an upper gate type or a bottom gate type thin film transistor. The sub-gate structure may include an upper sub-gate and/or a bottom sub-gate. The upper sub-gate overlays the channel region, drain offset and drain regions through an insulation layer. The bottom sub-gate underlies the channel region, drain offset and drain regions through an insulation layer. The sub-gate is applied with the same voltage or less as the drain voltage thereby permitting a relaxation of a high field concentration caused at a drain junction to be realized. This may provide a reduction of a leakage current and a security of a high ON-current.

The characterization of hot carrier damage in p-channel transistors

Abstract: Damage in surface channel p-MOS transistors arising from hot-carrier stress is examined using a recently proposed lifetime extraction method. It is shown that the p-MOS behavior with respect to hot-carrier stress runs counter to that of n-MOS transistors in many respects and has to be considered separately. Not only are the well-known post-stress gains in drive current obtained for p-MOS transistors, but also the measurement of the I-V characteristics with the stress damage at the source and drain ends shows effects opposite to those of n-MOS devices. This is attributed to coulombic screening by the channel charge. Stressing transistors in inverter-like and pass-transistor-like modes are also discussed, and it is found that p-MOS transistors are much more sensitive to pass-transistor-like damage than n-channel devices, due to increased channel length shortening in the pass transistor mode. It is shown that whereas at long gate lengths (>0.5 mu m) the degradation is limited to drain current changes, at shorter channel lengths ( >

Drain-induced barrier lowering in buried-channel MOSFET's

Abstract: In the literature, it is unclear whether or not buried-channel (BC) MOSFETs are less resistant to drain-induced barrier lowering than surface-channel MOSFETs. The authors clarify this confusion and experimentally demonstrate the relationship between the threshold voltage and channel length reduction for normally-on (inverting) BC-MOSFETs. The results are compared with similar measurements on surface-channel MOSFETs. It is shown that BC-MOSFETs are more prone to drain-induced barrier lowering than surface-channel MOSFETs. A simple analytic model is derived for the subthreshold current in small-geometry BC-MOSFETs. The model shows good agreement with experimental measurements and with subthreshold currents obtained using a two-dimensional numerical simulator. >

Field-effect transistor with structure for suppressing hot-electron effects, and method of fabricating the transistor

Abstract: A polysilicon gate (42) of an N-channel MOSFET (40) includes a P+ doped central portion (42a), and N+ doped lateral portions (42b,42c) which face an N-type source (24c) and drain (26c) respectively. An N-type dopant is implanted into the surface portion of a P-type channel region (18) to reduce the surface doping and adjust the transistor threshold voltage to approximately 0.8 volts. The lowered channel doping reduces the electric field at the drain (26c) and suppresses injection of hot electrons from the drain (26c) into the gate oxide (14), and also reduces the electric field across the gate oxide (14) and suppresses charging thereof by hot electrons. N-type and P-type graded strata (26a,26b) are formed between the drain (26c) and substrate (12) and create two reverse biased diode junctions which block flow of drain current from the channel region (18), thereby eliminating the creation of hot electrons and impact ionization in the bulk portion of the drain diode, and channel charge carriers through the surface portion of the channel region (18). The surface portions of the channel region (18), drain (26c) and graded strata (26a,26b) are shorted together to form a shorting surface channel through which the charge carriers are constrained to flow.

Impact of radiation-induced nonuniform damage near MOSFET junctions

Abstract: Laterally nonuniform distributions of radiation-induced oxide charge and interface traps near MOSFET junctions have been found in a variety of samples. As revealed by three independent measurement techniques, the degree of nonuniformity depends strongly on the process technology. Such lateral nonuniformity could arise from the lateral variation of the oxide field near the channel edges during irradiation and the different diode properties in these regions compared to those in the main channel region. These channel edge effects can significantly affect MOSFET device parameters such as the threshold voltage, transconductance, channel resistance, and effective channel length. This is especially the case for submicron devices. Results from computer simulation indicate that the edge damage alone could contribute to a major portion of the transconductance degradation in irradiated submicron devices. >

Linear voltage-controlled resistance element

Abstract: The channel resistance of a MOSFET is made independent of VS-VD by maintaining the ends of the gate electrode (24) adjacent the source (20) and drain (22) regions at an offset voltage with respect to the source and drain regions, respectively, and by maintaining the portions of the body regions adjacent to the source and drain regions at another offset voltage with respect to the source and drain regions, respectively. In this manner, VS-VD appears across the channel, across the gate, and across the body region beneath the channel. The resulting linear voltage drops along each of the three causes the channel-to-gate and channel-to-body potentials to be constant along the entire length of the channel, thereby avoiding variations in the number of carriers, mobility variations and body effect in the channel.

A simple two-dimensional model for subthreshold channel-length modulation in short-channel MOSFETs

Abstract: A physical yet simple model that describes subthreshold channel-length modulation and its complex relationship with drain-induced barrier lowering (DIB) in short-channel MOSFETs is derived. The underlying quasi-two-dimensional analysis produced a V/sub DS/-independent value for the modulated channel length in weak inversion, which can be used to simplify and correct subthreshold current simulation. The model, supported by numerical device simulation, further gives insight regarding how channel-length modulation scales with structural parameters. >

Comparison of Measurement Techniques for Gate Shortening in Sub-Micrometer Metal Oxide Semiconductor Field Effect Transistors

Abstract: In this paper, various methods of evaluating the electrical channel length change (or gate shortening) as a result of applied gate voltage in sub-micrometer metal oxide semiconductor field effect transistors (MOSFETs) are investigated and the method best suited for such short channel length devices is reported. Studies were performed on n-channel transistors (n-MOSFETs) fabricated using X-ray and optical lithography and having channel lengths in the range of 0.4 to 4 µm and 1.5 to 10 µm respectively. The effective channel lengths were extracted from the current-voltage (I-V) measurements. The measurements were made for different low and high sets of gate voltages. In comparing various methods it was found that the method due to Terada and Muta, and Chern et al. gave accurate results consistently for short channel MOSFETs, whereas the Whitfield method gave accurate results only for larger channel length MOSFETs. The accuracy of the Whitfield method is sensitive to applied gate voltage during I-V measurements. The Peng and Afromowitz method is unsuitable for finding the effective channel length of sub-micrometer MOSFETs especially if the MOSFETs have high values of external resistance.

A physical poly-silicon thin film transistor model for circuit simulations

Abstract: This paper presents a poly-silicon thin film transistor model for circuit simulations. The drain current model includes the effects of hot carriers, drain induced barrier lowering (DIBL), channel length modulation (CLM), and gate induced drain leakage (GIDL). The capacitance model is weakly linked to the drain current and its derivatives. This model has been implemented in a SPICE simulation and experimental results are compared. >

Gate recessed (GR) MOSFET with selectively halo-doped channel and deep graded source/drain for deep submicron CMOS

Abstract: A new recessed channel MOSFET, Gate Recessed MOSFET, is proposed to improve the reliability and the performance of deep submicron devices. GR-MOSFET is designed to have a lateral doping profile of S/D and channel gradually decreasing near both channel ends. This doping profile is obtained by selective doping of the channel and S/D without counter-doping and results in eliminating the tradeoff between DIBL (drain-induced barrier lowering) and hot carrier effects. The fabricated 0.25 /spl mu/m GR-MOSFET with 10 nm gate oxide has exhibited 15% higher transconductance, 10% increased saturation current at V/sub D/=V/sub G/=3.3V, 1 V higher BV/sub DSS/ and 6 times less substrate current compared with a LDD-MOSFET of the same effective gate length. >

Differential current source circuit in DAC of current driving type

Abstract: A differential current source circuit includes three P-channel MOSFETs and two N-channel MOSFETs. Each source of first and second P-channel MOSFETs is connected to a power supply, and a bias voltage is applied to each gate of the MOSFETs. A current path of the first N-channel MOSFET is connected between a drain of the first P-channel MOSFET and a ground. A current path of the third P-channel MOSFET is connected between a drain of the second P-channel MOSFET and a current output terminal. A gate of the third P-channel MOSFET is connected to the drain of the first P-channel MOSFET. One end of a current path of the second N-channel MOSFET is connected to a connecting point of the first P-channel and first N-channel MOSFETs, and the other end is connected to a connecting point of the second P-channel and third P-channel MOSFETs. A digital signal is applied to a gate of the second N-channel MOSFET.

Device model of mosfet and parameter extraction method

Abstract: PURPOSE: To provide a high-accuracy modeling method in a wide gate-voltage region and in a wide gate-length range as the drain current model of a MOSFET, for current simulation, which is used to design an LSI. CONSTITUTION: A drain current is expressed by an analytical-expression model whose constituent elements are composed of a mobility which is dependent on a threshold voltage, on a diffused layer resistivity and on a gate voltage and of a gate-diffusedlayer overlap length which is dependent on the gate voltage. In a parameter extraction method, a model parameter for the constituent elements is decided in such a way that the gate-voltage-dependence of the inclination ρ of channel resistance-to-gate length dependence near a part at a drain voltage of zero and of a channel resistance γ at a gate length of zero is measured, that the mobility is decided by the reciprocal number of diffused-layer resistivities γ o , ρ at ρ of zero and that the gate-diffused-layer overlap length is decided by an expression of (γ-γ o )Vge/ρ. COPYRIGHT: (C)1995,JPO

Threshold voltage leading method

Abstract: PURPOSE:To correctly lead a threshold voltage of a fine field effect transistor of which effective channel length and effective channel width are unknown with respect to a drain voltage change by setting a gate voltage, which makes minimal the difference characteristic of second order of a logarithmic value of a drain current for the gate voltage to a threshold voltage. CONSTITUTION:A voltage Vgs with reference to source is impressed to a gate terminal and a drain current ids is measured while Vgs is increased from 0. (1 to 3) A logarithmic value of the selected drain current is obtained to search difference of second order of the drain current in regard to the gate voltage. (4) A gate voltage which makes minimal the value of the difference of second order is obtained as a threshold voltage. (5) Thereby, the correct threshold value can be obtained even when the drain voltage changes. Therefore, the threshold voltage of a fine field effect transistor of which effective channel length and effective channel width are unknown can be led correctly with respect to change of the drain voltage.

Effects Of The Velocity-Saturated Region On MOSFET Scaling

Abstract: Introduction One of the major issues in constructing MOSFET scaling scenarios is the velocity saturation. For its quantitative evaiuation, a simple and accurate drain current formula, deduced from experimental data, is presented, together with its physical background. Using this formula, it is shown that the 1engi.h of the velocity-saturated region is a crucial parameter for considering MOSFET scaling.

A Physical Poly-Silicon Thin Film Transistor (TFT) Model for Circuit

Abstract: This report presents a poly-silicon thin film transistors model for circuit simulations. The drain current model includes the effects of hot carrier, drain induced barrier lowering (DIBL), channel length modulation (CLM), and gate induced drain leakage (GIDL). The capacitance model is linked to the drain current and its derivatives. This model has been implemented in SPICE. Simulation and experimental results are compared.

A nonpinchoff gradual channel model for deep-submicron MOSFET's

Abstract: A drain current model for a short-channel MOSFET, which is named the nonpinchoff model, is proposed. In this model, the effect of the horizontal electric field is precisely taken into account to solve the two-dimensional Poisson's equation. The pinchoff point, where the horizontal electric field tends to infinity in the conventional gradual-channel approximation, disappears in the nonpinchoff model, so that linear and saturation regions are smoothly connected. As a result, the ambiguity of the boundary between the linear region and saturation region in a short channel MOSFET can be understood using a single equation for the drain current. >

Fix to negative output conductance problem in BSIM2 model (MOSFET)

Abstract: The long-standing negative output conductance problem observed in the BSIM2 model, which causes convergence problems in circuit simulation, has been studied and resolved. The problem is identified to be related to both parameter extraction methodology and model equations. A redundant boundary condition in the saturation region for the optimization of output characteristics was found. A problematic channel length modulation equation also contributes to the problem. The fix to this problem not only eliminates the negative conductances in the simulated output characteristics of long-channel transistors but also preserves fits to output characteristics of short-channel transistors. The fix, at the same time, speeds up the parameter extraction process by 20% by eliminating five of the model parameters. >

A novel method to determine gate-drain overlap in sub-micron transistors

Abstract: This paper describes a novel method to determine the gate-drain overlap in a sub-micron channel length transistor under circuit operating conditions The method essentially entails applying 500 ns wide square wave pulses to the MOSFET drain and measuring the drain current response as determined by the gate coupling which, in turn, is determined by the gate-drain overlap capacitance After obtaining an accurate DC current model, the pulse measurements are matched with SPICE simulations to determine the accurate value for total lateral diffusion >

Detailed Analysis of Buried Oxide Degradation Induced by Hot-Carrier Injection

Abstract: The degradations of the SIMOX buried oxide after either front channel stress in p-MOSFETs or back channel stress in n-MOSFETs are analyzed as a function of drain bias and correlated. It is found that this damage may be alleviated and the device lifetime extended over 10 years by scaling the drain bias below 3V.

Improved representation of channel-length modulation in junction field-effect transistors

Abstract: An improved expression to represent the channel-length modulation in JFET devices is proposed. The accuracy of the derived equation is proved by comparing the theoretical results with the results obtained from measurements and the standard SPICE JFET model, respectively. The precision of proposed channel-length modulation term is demonstrated on a simple test circuit by comparing the simulated and experimental harmonic distortion properties. Simulated and experimental plots of the total harmonic distortion against VDS are found to be in good agreement, while conventional SPICE simulation results significantly differ from actual behaviour at low values of VDS .

A new recessed gate MOSFET structure with the graded source/drain

Abstract: Summary form only given. A gate recessed MOS (GR-MOS) structure with the selectively halo-doped channel by boron implantation carried out after graded (source/drain) (S/D) formation is proposed. The S/D is formed without n/sup +/ counter-doping to the channel doping. Initial characterization results of GR-MOSFETs having a 0.25 mu m channel length are presented in comparison with the conventional lightly doped drain (LDD)-MOSFETs. It was verified that the new concept gives improved device characteristics over the LDD structure for a wide range of bias conditions and channel lengths, and renders the device design window wider in deep submicron devices. >

Memory arrangement with a read-out circuit for a static memory cell

Abstract: A memory arrangement that includes a static memory cell with two MOSFETs that are connected such that an input signal for setting the memory cell is applied to one MOSFET, and the output of the other MOSFET is connected to the input of the first MOSFET, so that one MOSFET is always conductive while the other is blocked. The two MOSFETs are connected with positive feedback. In each case, the gate electrode is connected to a voltage equal to half the battery voltage. The source electrode of the first (N channel) MOSFET forms the input of the memory cell. The drain electrode of the first MOSFET is connected to the source electrode of the second (P channel) MOSFET. The blocking resistance of the drain-substrate diode of the first MOSFET is greater than the blocking resistance of the source-substrate diode of the second MOSFET. Also, the output voltage of the first (N channel) MOSFET is greater than the sum of the gate voltage and the threshold voltage of the second (P channel) MOSFET.

Circuit for producing a constant voltage

Abstract: of EP0337747A circuit for producing a constant voltage comprises first and second MOSFETs, and first and second bias voltage producing devices. The first and second MOSFETs to which first and second input voltages are applied, respectively, are connected in series. The first bias voltage producing device produces a potential difference, which is equal to a threshold voltage of the first MOSFET, to be applied across drain and gate of the first MOSFET, and the second bias voltage producing device produces a potential difference, which is equal to a threshold voltage of the second MOSFET, to be applied across drain and gate of the second MOSFET, so that a wide range of an output voltage is produced at a connecting point of the first and second MOSFETs. Even more, the output voltage is stabilized in level, even if the threshold voltages fluctuate in a semiconductor device fabricating process.

A physical model including velocity overshoot for drain current of sub-0.15 /spl mu/m MOSFET's

Abstract: An analytical model is developed to describe the drain-current characteristics of small-geometry (i.e. sub-0.15 /spl mu/m) bulk MOSFET's including both non-local transport and 3D channel charge control. The model is used to investigate effects of velocity overshoot and subthreshold degradation on the performance and scaling of bulk Si MOSFET's. >