Showing papers on "Channel length modulation published in 1995"

Experimental investigation of a PtSi source and drain field emission transistor

Abstract: A p‐type PtSi source and drain, no ‘‘gap,’’ metal oxide semiconductor field effect transistor (MOSFET) has been successfully fabricated and experimentally investigated in detail down to 4.2 K. Gate curves (source current versus gate voltage) clearly show that, in the ‘‘on’’ state, the current flow mechanism from the source metal into the channel gradually changes from primarily thermal emission over the small ∼0.2 eV Schottky barrier to holes to completely field emission through the triangular Schottky barrier as the temperature is lowered below ∼100 K. Gate curves for different channel lengths also show minimal short channel effects down to 1.0 μm, in agreement with previous simulations. Drain curves (source current versus drain voltage) demonstrate that the drive current is comparable to that of a conventional MOSFET, and that the Schottky barrier is rendered transparent to the flow of holes when the device is strongly ‘‘on.’’

Extended drain resurf lateral DMOS devices

Abstract: A high voltage PMOS or NMOS transistor 7 has improved on-resistance by truncating gate field oxide 43 so that drain region 42 may be implanted closer to channel region 49 than possible otherwise. By shortening the physical distance d2 between drain 42 and channel region 49, the drain to source on-resistance of the high voltage device is reduced and the performance of high voltage device 7 is thereby improved.

Trench MOSFET with heavily doped delta layer to provide low on- resistance

Abstract: In a vertical trench MOSFET, a layer of increased dopant concentration is formed in a lightly-doped or "drift" region which separates the body region from the drain region of the MOSFET. The layer of increased dopant concentration denominated a "delta" layer, operates to spread out the current as it emerges from the channel of the MOSFET and thereby reduces the resistance of the MOSFET when it is turned on.

Local thinning of channel region for ultra-thin film SOI MOSFET with elevated source/drain

Abstract: An elevated source/drain structure is described in which the channel region is thinned by local oxidation and wet etch while the source/drain region remained thick. This structure achieves source/drain resistances as small as 300 ohm-μm for NMOS, which makes possible high drive currents in deep submicron thin-film SOI/MOSFET.

Compounded power MOSFET

Abstract: Provided is a compounded power MOSFET which has a high positive and negative withstand voltages for the drain terminal relative to the source terminal, and can be formed on a single chip based on the conventional fabrication process of power MOSFETs. Power MOSFETs 10 and 11 have their drains connected together, the MOSFET 10 has its source and gate used for the source terminal 0 and gate terminal 1, respectively, of the compounded power MOSFET 60, and the MOSFET 11 has its source used for the drain terminal 2. The compounded power MOSFET includes a voltage comparator 50 which drives the MOSFET 11 to turn off when the terminal 2 has a negative voltage, and a voltage transmitter 51 which is connected between the terminal 1 and the gate of the MOSFET 11 to block a current flowing from the terminal 2 to the terminal 1 by way of the circuit 50 and transfer the voltage of the terminal 1 to the gate of the MOSFET 11. The positive withstand voltage is provided by the MOSFET 10, and the negative withstand voltage is provided by the MOSFET 11.

Zero-temperature-coefficient biasing point of partially depleted SOI MOSFET's

Abstract: Experimental and analytical results of the front gate bias (V/sub GS/) and the drain current (I/sub DS/) with the drain voltage (V/sub DS/) of partially depleted (PD) SOI MOSFET at the Zero-Temperature-Coefficient (ZTC) point over a very wide temperature range (25-300/spl deg/C) are presented. Two distinct ZTC points are identified, one in the linear region and the other is in the saturation region. Additionally, the analysis takes into consideration the body effects, and mobility degradation with applied front gate bias. The analysis results are in excellent agreement with the experimental results. >

Theoretical and numerical comparison between DMOS and trench technologies for insulated gate bipolar transistors

Abstract: An accurate and comprehensive comparison between DMOS and Trench technologies for Insulated Gate Bipolar Transistors (IGBT) is presented. The study is performed using extensive two-dimensional numerical simulations and fundamental physical modeling. Various phenomena such as the influence of the channel density on the forward voltage drop and the effect of the channel mobility degradation on the on-state characteristics have been the object of controversial studies. The analysis performed here describes rigorously these phenomena and accounts for new physical effects such as the channel length modulation and PIN diode carrier dynamics. It is concluded that at relatively high voltage and high current densities (>100 A/cm/sup 2/) an optimally designed Trench IGBT results in significant theoretical advantages over its conventional DMOS variant, mainly due to an increased packing density, PIN diode effect, reduced latch-up current density and elimination of the JFET effect. >

Three-dimensional analytical subthreshold models for bulk MOSFETs

Abstract: Three-dimensional device-physics-based analytical models are developed for subthreshold conduction in uniformly doped small geometry (i.e., simultaneously short channel and narrow width) bulk MOSFETs, for various isolation schemes. Inverse-narrow width effects, where the threshold voltage decreases with decreasing channel width, are predicted by the model for trench isolated MOSFETs. For LOGOS isolated MOSFETs, conventional narrow width effects, where the threshold voltage increases due to decreasing channel width, are predicted. The narrow width effects are found to be comparable to the short channel effects in the absence of significant applied drain biases. However, for larger drain biases, the short channel effects outweigh the narrow width effects due to the weaker potential perturbation at the device width edges compared to the drain end. Unlike the threshold voltage, the subthreshold swing of the device is found to increase with reduced device dimensions regardless of the isolation scheme since both conventional and inverse narrow width effects result in weaker control of the surface potential by the gate.

Fermi threshold field effect transistor including doping gradient regions

Abstract: A high saturation current, low leakage, Fermi threshold field effect transistor includes a predetermined minimum doping concentration of the source and drain facing the channel to maximize the saturation current of the transistor Source and drain doping gradient regions between the source/drain and the channel, respectively, of thickness greater than 300Å are also provided The threshold voltage of the Fermi-FET may also be lowered from twice the Fermi potential of the substrate, while still maintaining zero static electric field in the channel perpendicular to the substrate, by increasing the doping concentration of the channel from that which produces a threshold voltage of twice the Fermi potential By maintaining a predetermined channel depth, preferably about 600Å, the saturation current and threshold voltage may be independently varied by increasing the source/drain doping concentration facing the channel and by increasing the excess carrier concentration in the channel, respectively A Fermi-FET having a gate insulator thickness of less than 120Å, and a channel length of less than about 1 μm can thereby provide a P-channel saturation current of at least 4 amperes per centimeter of channel width and an N-channel saturation current of at least 7 amperes per centimeter of channel width, with a leakage current of less than 10 picoamperes per micron of channel length using power supplies of between 0 and 5 volts

Self-aligned dual gate MOSFET with an ultranarrow channel

Abstract: A dual gate field effect transistor with an ultra thin channel of substantially uniform width formed by a self-aligned process utilizing selective etching or controlled oxidation between different materials to form a vertical channel extending between source and drain regions, having a thickness in the range from 2.5 nm to 100 nm.

A physically based C/sub /spl infin//-continuous model for small-geometry MOSFET's

Abstract: An explicit single-piece MOSFET model is derived from a surface potential formulation. The model covers small-geometry effects, like mobility reduction, channel-length modulation, carrier velocity saturation, and short- and narrow-channel effects. Good agreement has been found with measured characteristics. Furthermore, the DC current calculated using the new model shows smooth transitions through all regions of operation. Therefore the convergence when employed in circuit simulation will be improved. >

Boron penetration to suppress short channel effect in P-channel device

Abstract: A method for forming a set of p-channel devices with enhanced n-doping and penetration of boron into the channel region between the source and drain regions, thereby creating channel length independent p-channel threshold voltage behavior. Long channel and short channel transistors have approximately equal threshold voltages as (a) short channel effect is reduced with increased n-doping in short channel transistors (where boron penetration has little effect), and (b) the effects of boron penetration and increased n-doping are offset in longer channel transistors.

Vertical MOS Transistors with 70nm Channel Length

Abstract: Vertical nMOS transistors with channel lengths down to 70nm and thin gate oxides have been fabricated using LPCVD epitaxy for the definition of the channel region instead of fine line lithography. The devices show drain current and transconductance values comparable to very advanced planar transistors. For the shortest channel length a stronger increase of current is observed and is attributed to ballistic and floating substrate effects. Besides high saturation currents due to very short channel lengths a higher integration density seems to be feasible using this vertical transistor technology.

Method of large angle tilt implant of channel region

Abstract: A channel region formation process in field effect transistors directed toward reducing threshold voltage sensitivity to variations in gate length resulting from manufacturing techniques. A polysilicon gate is formed over the substrate and a channel region is subsequently implanted at a large angle measured from perpendicular to the substrate. Large angle implantation results in a non-uniform doping concentration in the channel region, improving threshold voltage sensitivity. Improvement can also be seen in other parameters, including source-drain current, substrate current, leakage current, magnification factor, and hot electron channel injection efficiency.

Circuit arrangement for regulating the load current of a power MOSFET

Abstract: In a circuit arrangement for regulating the load current of a power MOSFET, the drain-source voltage of the power MOSFET is imaged onto the input of a second MOSFET connected between a gate terminal and source terminal of the power MOSFET. When the input voltage exceeds the cut-off voltage, then the gate-source voltage at the power MOSFET is regulated back to a value that corresponds to the sum of the cut-off voltages of the second MOSFET and a third MOSFET. The gate terminals of third MOSFET and the power MOSFET are connected to one another.

Reverse short channel effect and channel length dependence of boron penetration in PMOSFETs

Abstract: The anomalous increase in reverse-short-channel effect of PMOSFETs, in the presence of boron penetration from the gate, is examined here. Based on an extensive simulation and experimental study, we demonstrate that the degree of boron penetration is a function of the channel length and that long channel transistors are more susceptible to boron penetration compared to short channel devices. This leads to the observed decrease in threshold voltage with increasing channel length and hence, an enhanced reverse-short-channel-like behavior in PMOSFETs. Using length scale arguments, we propose that silicon interstitial absorption into the gate oxide is responsible for blocking boron penetration at the edges of the channel as compared to the middle, thus making the short channel length transistors more immune to boron penetration as compared to long channel length ones.

A model for dual-channel high electron mobility transistors

Abstract: In this paper, a technique is developed to calculate the total charge of a dual channel HEMT. This technique is able to successfully predict the gradual saturation of charges in the device. The current voltage characteristics and the transconductance of the device are derived including the effect of channel length modulation as well as parasitic source and drain resistances. The theoretical predictions of the model are compared with experimental data and shown to be in good agreement.

Method for extracting deep submicrometre MOSFET parameters

Abstract: As the MOSFET channel length shrinks to 0.1 µm, the influence of the lateral field on the device characteristics becomes increasingly important even at low drain voltage (10 mV). The authors present a new method which takes into account the effect of the lateral field to extract the deep submicrometre MOSFET parameters such as threshold voltage, effective channel length, effective mobility and parasitic series resistance.

Physical model of threshold voltage in silicon MOS transistors including reverse short channel effect

Abstract: A physically based model for the MOSFET threshold voltage accounting for the reverse short channel effect is proposed. This threshold voltage model, which incorporates the inhomogeneous transverse and longitudinal doping profiles as well as the conventional charge sharing short channel effect, has been successfully tested on several submicronic technologies with various channel lengths.

Self-aligned anti-punchthrough implantation process

Abstract: The invention relates to a method of forming an improved MOSFET device structure for use in ultra large scale integration devices. A local self-aligned anti-punchthrough region is formed directly under the gate electrode using ion implantation. The local anti-punchthrough region reduces the expansion of the depletion region in the channel and thereby increases the punchthrough voltage. The local anti-punchthrough region is self-aligned with the gate electrode and source/drain region so that critical spacings are maintained even for sub micron devices. Channel mobility is not degraded and the source and drain junction capacitances are reduced. The invention can be used in either N channel or P channel MOSFET devices, and in either LDD (light doped drain) or non-LDD devices.

New experimental findings on hot carrier effects in sub-0.1 μm MOSFET's

Abstract: The behaviors of the substrate current and the impact ionization rate are investigated for deep submicron devices in a wide temperature range. New important features are shown for the variations of the maximum substrate current as a function of applied biases and temperature. It is found that the gate voltage V/sub gmax/, corresponding to the maximum impact ionization current conditions, is quasi-constant as a Function of the drain bias for sub-0.1 /spl mu/m MOSFET's in the room temperature range. At low temperature, a substantial increase of V/sub gmax/ is observed when the drain voltage is reduced. It is also shown that, although a significant enhancement of hot carrier effects is observed by scaling down the devices, a strong reduction of the impact ionization rate is obtained for sub-0.1 /spl mu/m MOSFET's operated at liquid nitrogen temperature in the low drain voltage range. >

Extraction of gate dependent source/drain resistance and effective channel length in MOS devices at 77 K

Abstract: A new extraction technique for obtaining the parasitic source/drain resistance and the effective channel length of an MOS device at 77 K is presented. Unlike previous methods, both parameters are assumed to vary with the gate voltage. This results in positive and physically meaningful results at any temperature. Simulation results show that, in non-LDD devices, the source/drain resistance decreases and the effective channel length increases with gate bias, indicating that the gate dependence of both parameters is inherent to MOS devices. >

Current-voltage model of short-channel MOSFETs operated in the linear region

Abstract: A new analytic MOSFET current model in the linear region is developed by using the pseudo-two-dimensional approximation. The model physically accounts for the threshold voltage reduction with decreasing channel length. In the model a set of device parameters can be used for devices with different channel lengths. The model has been applied to study the current of lightly doped drain (LDD) MOSFETs with drawn channel length of 0.6 to 20 μm, and a good fitting has been achieved between the experimental data and the model.

Experimental evidence for statistical‐inhomogeneous distributed dopant atoms in a Si metal‐oxide‐semiconductor field‐effect transistor

Abstract: We have experimentally and analytically studied the statistically inhomogeneous distributed dopant atoms in silicon metal‐oxide‐semiconductor field‐effect transistors (MOSFETs) with very small dimensions, by investigating the threshold voltage characteristics. By interchanging the source and the drain terminals of an individual MOSFET in an 8192 MOSFET array within an area of less than 0.7 mm2, it was found that the asymmetry of the threshold voltage Vth of a MOSFET is observed only at high drain bias, and continues to increase with increasing the drain bias and scaling the channel length down. These results can be quantitatively explained by our analytical model in which the dopant atoms are inhomogeneously distributed along the channel and statistically fluctuated in the local region of the channel among 8192 MOSFETs.

Threshold voltage sensitivity of 0.1 /spl mu/m channel length fully-depleted SOI NMOSFET's with back-gate bias

Abstract: We found threshold voltage sensitivity to silicon thickness variation in 0.1 /spl mu/m channel length fully-depleted SOI NMOSFET's can be reduced with lightly-doped channel and back-gate bias. However, after the back-interface is accumulated, the reduction is small and threshold voltage roll-off due to high drain bias increases. >

Method of making FET with two reverse biased junctions in drain region

Abstract: A polysilicon gate (42) of an N-channel MOSFET (40) includes a P+ doped central portion (42a), and N+ doped lateral portions (42b,42c) which face an N-type source (24c) and drain (26c) respectively. An N-type dopant is implanted into the surface portion of a P-type channel region (18) to reduce the surface doping and adjust the transistor threshold voltage to approximately 0.8 volts. The lowered channel doping reduces the electric field at the drain (26c) and suppresses injection of hot electrons from the drain (26c) into the gate oxide (14), and also reduces the electric field across the gate oxide (14) and suppresses charging thereof by hot electrons. N-type and P-type graded strata (26a,26b) are formed between the drain (26c) and substrate (12) and create two reverse biased diode junctions which block flow of drain current from the channel region (18), thereby eliminating the creation of hot electrons and impact ionization in the bulk portion of the drain diode, and channel charge carriers through the surface portion of the channel region (18). The surface portions of the channel region (18), drain (26c) and graded strata (26a,26b) are shorted together to form a shorting surface channel through which the charge carriers are constrained to flow.

Switching device including power MOSFET with internal power supply circuit

Abstract: An N-channel power MOSFET includes a storage capacitor and a pair of diodes connected between the gate and drain terminals, respectively, and the capacitor. Since at any given time the voltage at either the drain or the gate of the MOSFET is high, a charge is maintained on the storage capacitor as the MOSFET is switched on and off. The charge stored on the capacitor yields an output voltage which may be used to power a gate drive circuit or other components within or outside the MOSFET.

Electrical gate length measurement test structure for short channel MOSFET characteristics evaluation

Abstract: The electrical characteristics and gate lengths of individual MOSFETs are evaluated by a test structure with a Kelvin pattern as the gate electrode. The gate length measurement by SEM can be substituted by the electrical measurement using this test structure. Excellent correspondence is obtained between the threshold voltage lowering in the short channel region and the electrically measured gate length. Furthermore, the precision of drain-to-gate overlap length is improved by applying the effective channel length extraction method to the electrically measured gate length instead of the commonly used designed gate length.

An improved quasi two-dimensional model for short-channel MOSFETs

Abstract: An improved quasi two-dimensional model for the electric field in the drain region, and its subsequent application in the modeling of the strong-inversion region current, the drain conductance, and the substrate current for a short-channel MOSFET are presented in this paper. This work also considers the variation of the surface potential as a function of the gate bias beyond strong-inversion, and the variation of the lateral electric field as a function of depth into the bulk, in addition to the other second-order effects accounted for in the literature. These two additional modifications resulted in a continuous drain conductance curve with respect to the drain-to-source voltage at the onset of saturation point, which is a significant contribution of this work. Previous work attributed this discontinuity to the modeling of drain/source series resistance as lumped elements, which our work shows to be not entirely correct. A simple method is proposed to calculated the drain conductance. The model is also used to obtain the substrate current by numerically integrating the electric field in the pinch-off region without introducing any extra fitting parameter.

Circuit for controlling pulse output stage e.g. for pulse diode laser

Abstract: The invention relates to a circuit configuration for driving a pulse output stage which comprises a MOSFET power stage and a drive circuit (5) which is connected to the drain of the MOSFET (1) as the sole power supply. The parameters of the circuit configuration are designed in such a manner that the voltage drop on the drain of the MOSFET (1) does not exceed the admissible maximum voltage at the gate of the MOSFET (1). The supplied current flowing from the drain of the MOSFET to the drive circuit preferably contributes to the load current.