Showing papers on "Channel length modulation published in 1996"

Thermal noise modeling for short-channel MOSFETs

Abstract: An analytical formulation of the thermal noise in short-channel MOSFETs, working in the saturation region, is presented. For the noise calculation, we took into account effects like the field dependent noise temperature and mobility, the device geometry and the channel length modulation, the back gate effect and the velocity saturation. The derived data from the model are in good agreement with reported thermal noise measurements, regarding the noise bias dependence, for transistors with channel lengths shorter than 1 /spl mu/m. Since the present thermal noise models of MOS transistors are valid for channel lengths well above 1 /spl mu/m, the proposed model can be easily incorporated in circuit simulators like SPICE, providing an extension to the analytical thermal noise modeling suitable for submicron MOSFETs.

A novel CMOS current conveyor realization with an electronically tunable current mode filter suitable for VLSI

Abstract: A novel CMOS realization of the second generation current conveyor is given. A circuit which compensates the voltage offset due to channel length modulation effect is then developed. The CCII is then used to realize a new electronically tunable low-pass-band-pass filter suitable for VLSI. Simulation results taking the second-order effects into account indicate the excellent performance of both the CCII circuit and the filter over a wide dynamic range.

Vertical MOS transistors with 70 nm channel length

Abstract: Vertical nMOS transistors with channel lengths down to 70 nm and thin gate oxides have been fabricated using LPCVD epitaxy for the definition of the channel region instead of fine line lithography. The devices show drain current and transconductance values comparable to very advanced planar transistors. For the shortest channel length a very strong increase of saturation current is observed and is attributed to V/sub t/ shift and floating substrate effects. Moreover, transconductance may indicate ballistic overshoot. Besides high saturation currents due to very short channel lengths higher integration density seems to be very attractive for special applications.

Short-channel effect immunity and current capability of sub-0.1-micron MOSFET's using a recessed channel

Abstract: Sub-0.1-/spl mu/m planar and gate recessed MOSFET's are investigated using both drift-diffusion and Monte Carlo simulations. In nonplanar devices, the influence of the gate corner explains that the threshold voltage roll-off can be almost suppressed. A steeper subthreshold slope (low swing) is also obtained for a channel length shorter than 50 nm when the recessed channel MOSFET is compared to its planar counterpart. The influence of the corner effect on high-current performances is also considered in relation with the electric field profile along the Si/SiO/sub 2/ interface.

Method of making self-aligned dual gate MOSFET with an ultranarrow channel

Abstract: A dual gate field effect transistor with an ultra thin channel of substantially uniform width formed by a self-aligned process utilizing selective etching or controlled oxidation between different materials to form a vertical channel extending between source and drain regions, having a thickness in the range from 2.5 nm to 100 nm.

CMOS voltage controlled floating resistor

Abstract: A new CMOS floating linear resistor circuit with a wide linearity range is proposed. The circuit employs 14 transistors all operating in the saturation region. A modified circuit which employs one more transistor, such that it is threshold voltage independent, is also given. PSPICE simulations taking into account the second order effects due to the channel length modulation and mobility degradation are given.

An effective channel length determination method for LDD MOSFETs

Abstract: We propose a definition of MOSFET effective channel length (L/sub EFF/), that provides a method of determining L/sub EFF/ as a constant, and external resistance (R/sub EXT/) virtually as a constant, even for lightly doped drain (LDD) transistors. A unified relationship between this L/sub EFF/ and MOSFET drive current (linear and saturation) that is common to a wide range of drain structures was confirmed. Therefore, the L/sub EFF/ is useful, not only for compact analytical models, but also as an index of MOSFET performance applicable to both single drain and LDD devices. The dependence of the channel length on the source/drain structure was clarified by introducing the concept of local contribution to channel length. The L/sub EFF/ varies, even if the metallurgical channel length is fixed, depending on the design of the source/drain.

Fabrication of a New Si Field Emitter Tip with Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) Structure

Abstract: A current-controllable silicon field emitter tip with a metal-oxide-semiconductor field-effect transistor (MOSFET) structure is fabricated. The device has a simple structure in which a conical Si tip is made in the drain region of a MOSFET. The gate performs two roles; one is that of a conventional extraction gate and the other is that of a control gate for the drain current supplied to the tip. The fabrication process is very simple. In order to form n-type regions for the source and drain, only two steps including a self-aligned ion implantation were added to the conventional silicon tip fabrication process. Experimental results showed that the emission current was well controlled and stabilized by the drain current of the MOSFET. Stable emission of about 0.8 µA was obtained with a single tip. We also discuss a dual-gate MOSFET for further extension of the fabrication process introduced.

Fermi-threshold field effect transistors including source/drain pocket implants and methods of fabricating same

Abstract: A Fermi-FET, including but not limited to a tub-FET, a contoured-tub Fermi-FET or a short channel Fermi-FET includes a drain extension region of the same conductivity type as the drain region and a drain pocket implant region of opposite conductivity type from the drain region The drain pocket implant region acts as a drain field stop to reduce or prevent drain-to-source field reach-through Reduced low drain field threshold voltage, significantly reduced drain induced barrier lowering and reduced threshold dependence on channel length may be obtained, resulting in higher performance in short channels

Stable output bias current circuitry and method for low-impedance CMOS output stage

Abstract: A CMOS output circuit including a differential error amplifier (3) is operated to provide a stable quiescent bias current in an output MOSFET by causing a first current equal to a threshold voltage of a P-channel reference MOSFET (M1) divided by the resistance of a reference resistor (R1) to flow through an N-channel current mirror control MOSFET (M4). A first N-channel current mirror output MOSFET (M6) having a gate coupled to the gate of the N-channel current mirror control MOSFET (M4) and a drain coupled to a drain of the P-channel reference MOSFET (M1) causes a second current proportional to the first current to flow through the P-channel reference MOSFET (M1). The first current is controlled in response to feedback from the P-channel reference MOSFET (M1). A bias current in an error amplifier (3) is controlled in response to the N-channel current mirror control MOSFET (M4). The bias current in the error amplifier and the resistances of first (R2) and second (R3) resistive load devices of the error amplifier are scaled to produce a drive voltage which applies a gate-to-source quiescent bias voltage to a P-channel pull-up MOSFET (M11) which is substantially equal to and tracks with the gate-to-source voltage of the reference MOSFET (M1).

Method for reduction of reverse short channel effect in MOSFET

Abstract: This invention describes a manufacturing method for MOSFET devices that are free from reverse short channel effect usually found in such devices made by prior art processes. In contrast to the prior art process sequence, the channel implant is made after the source and drain already formed by implantation and its damage already annealed out. The enhanced diffusion of the channel implant, caused by damage generated point defects and responsible for the reverse short channel effect, is therefore avoided. The channel implantation uses high energy ions to penetrate through the polysilicon gate, forming a threshold voltage adjustment and punch-through barrier layer under the gate. The channel implant through the source/drain regions is deeper than the source/drain junctions so that the junction capacitance is reduced in comparison with the prior art.

Profiling interface traps in MOS transistors by the DC current-voltage method

Abstract: Position profiling the interface trap density along the channel length of metal-oxide-silicon transistors by the Direct-Current Current-Voltage method is illustrated for five density variations: zero, peaked in drain junction space-charge layer, constant in channel, nonconstant in channel, and peaked in drain junction space-charge layer and nonconstant in channel. The interface trap densities were monitored by MOS transistor's d.c. body current and the density profiles were obtained from the body-drain and body-source differential conductance versus drain or source bias voltage. An experimental demonstration is given for a 1.6 /spl mu/m n-channel Si MOS transistor with about 10/sup 11/ traps/cm/sup 2/ generated by channel hot electron stress.

Device parameter optimization for reduced short channel effects in retrograde doping MOSFET's

Abstract: A simple technique to optimize the device parameters of the retrograde channel doping MOSFET to minimize short channel effects for a constant threshold voltage is presented in this work. The results indicate that the highest possible substrate doping does not necessarily result in minimum short channel effects.

A novel technique to determine the gate and drain bias dependent series resistance in drain engineered MOSFETs using one single device

Abstract: A new measurement method is explained for the extraction of the source and drain series resistance of drain engineered MOSFETs from their low frequency ac characteristics as a function of gate and drain bias using only one single MOSFET. Experimental results indicate, the effect of drain voltage dependent series resistance is relevant both in the ohmic and in the saturation region of the MOSFET. In addition the new measurement method is extended in such a way that it can be used to measure the series resistance as a function of gate bias only at low drain bias. Comparison of this single transistor measurement technique with other methods, needing a set of identical transistors with different channel lengths, shows that our method gives equal results. Finally attention is also given to the modeling of the series resistance in the ohmic and saturation region. For both regions simple, accurate compact model expressions have been derived.

Decoder circuit with short channel depletion transistors

Abstract: A decoder circuit formed on an integrated circuit substrate including at least one short channel depletion transistor having a low resistance path formed between the source and the drain regions. The low resistance path is provided by an implant into the channel region that forms a depletion channel wherein the channel region has a length less than a length of a channel region of transistors in the decoder circuit that handle input/output voltage levels for the decoder circuit.

Method of making semiconductor-on-insulator device with closed-gate electrode

Abstract: A body-tied MOSFET (14) is used in a protection circuit (10) of an SOI device (20) where the MOSFET's drain regions (38) lie outside MOSFET's closed-gate electrode (34). Electrical characteristics of the body-tied MOSFET (14) can be changed by varying the ratio of the total source region area to the total body-tied region area (tie frequency). The total electrical device width is the sum of the individual source region (36) widths. More charge can be placed on the drain region (38) compared to a drain region on the inside because the interfacial area between the drain region and channel region is larger. The device (20) can be formed without having to develop new processing steps or use marginal processing steps. Body ties to an underlying substrate are unnecessary.

Influence of channel doping-profile on camel-gate field effect transistors

Abstract: We report the performance of GaAs camel-gate FETs and its dependence on device parameters. In particular, the performance dependence on the doping-profile of a channel was investigated. In this study, one-step, bi-step, and tri-step doping channels with the same doping-thickness product are employed in camel-gate FETs, while keeping other parameters unchanged, For a one-step doping channel FET, theoretical analysis reveals that a high doping channel would provide a large transconductance which is suitable for logic applications. Decreasing the channel concentration increases the drain current and the barrier height. For a tri-step doping channel FET, it is found that the output drain current and the barrier height remain large and the relatively voltage-independent transconductance is also increased. These are the requirements for the large input signal power amplifiers. A fabricated camel-gate FET with a tri-step doping channel exhibits a large drain current density larger than 750 mA/mm and a potential barrier greater than 1.0 V. Furthermore, the relatively voltage-independent transconductance is as high as 220 mS/mm and the applied gate voltage is up to +1.5 V. A 1.5/spl times/100 /spl mu/m/sup 2/ device is found to have a f/sub t/ of 30 GHz with a very low input capacitance.

Unified physical I-V model including self-heating effect for fully depleted SOI/MOSFET's

Abstract: A physically based analytical I-V model that includes self-heating effect (SHE) is presented for fully depleted SOI/MOSFET's. The incorporation of SHE is done self-consistently in a fully closed form, making the model very suitable for use in circuit simulators. The model also accounts for the drain induced conductivity enhancement (DICE) and drain induced barrier lowering (DIBL), channel length modulation (CLM), as well as parasitic series resistances (PSR). Another advantage is the unified form of the model that allows us to describe the subthreshold, the near-threshold and the above-threshold regimes of operation in one continuous expression. A continuous transition of current and conductance from the linear to the saturation regimes is also assured. The model shows good agreement with measured data for a wide range of channel lengths (down to 0.28 /spl mu/m) and film thicknesses (94 nm-162 nm).

A novel 0.1 μm MOSFET structure with inverted sidewall and recessed channel

Abstract: To solve the problems of trade-off between the short channel effect and the performance enhancement of sub-quartermicrometer MOSFETs, we have developed a recessed channel MOSFET structure called ISRC (Inverted-Sidewall Recessed-Channel). The oxide thickness is 4 nm and the effective channel length is 0.1 /spl mu/m, which is the smallest Si-MOSFET ever reported in the recessed channel structures. The maximum saturation transconductance at V/sub D/=2 V is 446 mS/mm for the 0.1 /spl mu/m n-channel device. The threshold voltage roll-off is kept within 64 mV when the gate length varies from 1.4 /spl mu/m to 0.1 /spl mu/m and good subthreshold characteristics are achieved for 0.1 /spl mu/m channel device.

Scattering theory of the short channel MOSFET

Abstract: A simple, physical approach for modeling ultrasubmicron MOSFETs is introduced. The approach, based on scattering probabilities, produces analytical results that reduce to conventional ones for long channel devices but which apply to ballistic MOSFETs as well. The new model is related to conventional models, and issues such as the role of inversion layer mobility, velocity overshoot, and identifying the maximum saturated drain current, are addressed.

An accurate gate length extraction method for sub-quarter micron MOSFET's

Abstract: By comparing measured and simulated gate-to-source/drain capacitances, C/sub gds/, an accurate gate length extraction method is proposed for sub-quarter micron MOSFET's applications. We show that by including the 2-D field effect on the fringing capacitance, the polysilicon depletion and the quantum-well effects in the C/sub gds/ simulation, the polysilicon gate length, L/sub poly/, can be accurately determined for device lengths down to the 0.1 /spl mu/m regime. The accuracy of this method approaches that of cross-sectional TEM on the device under test, but without destroying the device. Furthermore, we note that as a result of accurate L/sub poly/ extraction, the source/drain lateral diffusion length, L/sub diff/, and effective channel length, L/sub eff/, can also be determined precisely. The accuracy of L/sub diff/ is confirmed by examining their consistency with experimentally obtained 2-D source/drain profile.

Effects of random MOSFET parameter fluctuations on total power consumption

Abstract: Intrinsic fluctuations in threshold voltage, subthreshold swing, saturation drain current and subthreshold leakage of ultra-small-geometry MOSFETs due to random placement of dopant atoms in the channel are examined using novel physical models and a Monte-Carlo simulator. These fluctuations are shown to pose fundamental barriers to the scaling of supply voltage and channel length and thus, to the minimization of power dissipation in multi-billion transistor chips of the future. In particular, using the device technology and the level of integration projections of the National Technology Roadmap for Semiconductors for the next 15 years, standard-maximum deviations of threshold voltage, drive current, subthreshold swing and subthreshold leakage are shown to escalate to 40-600 mV, 10-100%, 2-20 mV/dec. and 10-10/sup 8/%, respectively, in the 0.07 /spl mu/m, 0.9 V CMOS technology generation with 1.3-64 billion transistors on a chip. While these limits can be transcended to some degree by selecting optimal transistor width values larger than the channel length, the associated penalties in dynamic and static power, and in packing density demand novel MOSFET designs aimed at minimizing these fluctuations.

Drain current enhancement due to velocity overshoot effects and its analytic modeling

Abstract: The drain current enhancement due to the velocity overshoot effects is found to be due to the electron velocity enhancement at the source end. Based on this observation, a new analytic model is proposed and verified by two-dimensional (2-D) simulations and experiments. From the results of the verifications, we conclude that our model predicts the drain current enhancement due to the velocity overshoot effects reasonably well. The effects of the device parameters, such as gate oxide thickness and channel doping concentration, on the drain current enhancement ran be readily found in our model.

Modeling of hot-carrier stressed characteristics of submicrometer pMOSFETs

Abstract: In a p MOSFET, trapped electrons in the gate oxide due to hot-carrier stress reduce the effective channel length by inverting the surface from an n -type surface to a p -type surface and extend the p drain region. To describe the channel shortening, this paper presents a new analytical, physics-based I - V model for hot-electron damaged submicrometer p -type MOSFETs. The model was developed based on a pseudo-two-dimensional approach, it incorporates the effect of the spatial distribution of trapped electrons and can be used to calculate the degraded channel electric field and potential distribution. The model can also describe the time-dependence of degraded drain current with stress time.

Use of Indium and Gallium as P-Type Dopants in Si 0.1 µm MOSFETs

Abstract: Devices with a channel length of 0.1 µm, employing In and B as p-type channel dopants, were fabricated to investigate the short channel effect. In this study, the benefits of using In instead of B are investigated with respect to the suppression of the short channel effect, the gate quality, the mobility and the long channel threshold voltage value. It is concluded that the use of In causes no direct complications. The advantage of using In lies in the suppression of the short channel effect. In this way, the conventional planar bulk device employing In as a channel implant can be scaled further at least for one generation of metal oxide semiconductor transistors without loss in current driveability. The feasibility of Ga as an ultra shallow p-type extension is also investigated.

A new extraction algorithm for the metallurgical channel length of conventional and LDD MOSFETs

Abstract: A new extraction algorithm for the metallurgical channel length of conventional and LDD MOSFETs is presented, which is based on the well-known resistance method with a special technique to eliminate the uncertainty of the channel length and to reduce the influence of the parasitic source/drain resistance on threshold-voltage determination. In particular, the metallurgical channel length is determined from a wide range of gate-voltage-dependent effective channel lengths at an adequate gate overdrive. The 2-D numerical analysis clearly show that adequate gate overdrive is strongly dependent on the dopant concentration in the source/drain region. Therefore, an analytic equation is derived to determine the adequate gate overdrive for various source/drain and channel doping. It shows that higher and lower gate overdrives are needed to accurately determine the metallurgical channel length of conventional and LDD MOSFET devices, respectively. It is the first time that we can give a correct gate overdrive to extract L/sub met/ not only for conventional devices but also for LDD MOS devices. Besides, the parasitic source/drain resistance can also be extracted using our new extraction algorithm.

A comparative study of advanced MOSFET structures

Abstract: This work presents a comparative study of advanced MOSFET structures that have been proposed for around 0.1 /spl mu/m generation in the subjects of short-channel effect, drain saturation current, and relative gate delay. Our approach differs from other studies in that we emphasize compact analytical models and parametric comparison. These heuristic and analytic models are guided by experimental and simulational data. Based on these models, key device design parameters are extracted and compared. This approach provides good insight for device design, quick figure-of-merit, and a framework for analyzing a wide variety of MOSFETs. The devices in this study are : (a) uniformly-doped MOSFET, (b) delta-doped MOSFET, (c) pocket-implanted MOSFET, (d) SOI MOSFET, and (e) double-gated MOSFET. Their generic extensions cover almost every advanced MOSFET.

Unified physical I- V model of fully depleted SOI/MOSFETs for analog/digital circuit simulation

Abstract: An improved physical I-V model for fully depleted SOI/MOSFETs with channel lengths down to deep submicrometer range is presented. The model contains the following advanced features: precise description of the subthreshold, near-threshold and above-threshold regimes of operation using one single expression; precise description of I-V and G-V characteristics in the saturation region; continuous and smooth transition of the drain current and conductance from the linear to the saturation regime; extrinsic model expressions for devices with parasitic drain and source series resistances; inclusion of important short channel effects accounting for velocity saturation, drain induced barrier lowering (DIBL) and drain induced conductivity enhancement (DICE), channel length modulation (CLM), as well as the gate bias dependent mobility; a description of the floating body effect associated with drain breakdown. Inclusion of these features greatly improves the accuracy as well as the convergence properties and the calculating efficiency when using the model in circuit simulators. The present model agrees well with experimental results for a wide range of process and device parameters.

Determination of LDD MOSFET drain resistance from device simulation

Abstract: A simple, efficient and accurate technique for the determination of the drain resistance of LDD MOSFETs, using a two-dimensional device simulator, is presented. This method does not require the artificial introduction of constraints that would alter the normal operating conditions and geometry of the device. Comparison is made with a more elaborate technique, where the drain region is modelled as a network of resistances. For an appropriately chosen mesh size, good agreement to within 10% has been achieved for the two techniques. In terms of computational labour, the simple technique enjoys at least an order of magnitude advantage compared with the more elaborate model. The two techniques have also been used to study the dependence of the drain resistance on the gate and the drain bias, and to establish the accuracy over a broad bias range. An estimate is also made of the degradation of the drain resistance due to hot-carrier stress.

A 3D analytical model for threshold voltage of small-geometry MOSFET

Abstract: A three-dimensional analytical model for the threshold voltage is developed by solving Poisson's equation for trench-isolated MOSFET devices with uniform substrate doping. The analytical expression is the first developed to include the coupling effect of both the inverse narrow width effect (INWE) and short channel effect which result from the mutual modulation of the depletion depth of the small size device. An expression for surface potential distribution is also obtained which shows the enhanced surface potential at the edges of channel width due to the electric field fringing effect. To check the accuracy of the present model the results are compared with 3D MICROMOS Simulator [L. A. Akers and K. L. Hsueh, SIAM Tech. Abstr. 22a , xx (1985)]. Good agreements have been obtained for wide ranges of channel width and length.