Showing papers on "Channel length modulation published in 1998"

Device design considerations for double-gate, ground-plane, and single-gated ultra-thin SOI MOSFET's at the 25 nm channel length generation

Abstract: We present a simulation-based analysis of device design at the 25 nm channel length generation. Double-gate, ground-plane, and single-gated ultra-thin SOI MOSFET's are considered. Dependencies of short-channel effects on channel thickness and ground-plane bias are illustrated. Two-dimensional field effects in the gate insulator (high k) and the buried insulator (low k) in single-gate SOI are studied.

Full-band Monte Carlo investigation of hot carrier trends in the scaling of metal-oxide-semiconductor field-effect transistors

Abstract: A full-band Monte Carlo (MC) device simulator has been used to study the effects of device scaling on hot electrons in different types of n-channel metal-oxide-semiconductor field-effect transistor (MOSFET) structures. Simulated devices include a conventional MOSFET with a single source/drain implant, a lightly-doped drain (LDD) MOSFET, a silicon-on-insulator (SOI) MOSFET, and a MOSFET built on an epitaxial layer on top of a heavily-doped ground plane. Different scaling techniques have been applied to the devices, to analyze the effects on the electric field and on the energy distributions of the electrons, as well as on drain, substrate, and gate currents. The results provide a physical basis for understanding the overall behavior of impact ionization and gate oxide injection and how they relate to scaling. The observed nonlocality of transport phenomena and the nontrivial relationship between electric fields and transport parameters indicate that simpler models cannot adequately predict hot carrier behavior at the channel lengths studied (sub-0.3-/spl mu/m). In addition, our results suggest that below 0.15 /spl mu/m, the established device configurations (e.g. LDD) that are successful at suppressing the hot carrier population for longer channel lengths, become less useful and their cost-effectiveness for future circuit applications needs to be reevaluated.

Two-dimensional numerical simulation of Schottky barrier MOSFET with channel length to 10 nm

Abstract: We present simulation results of a silicon-based metal-oxide-semiconductor field-effect transistor (MOSFET), which has a structure similar to that of a conventional MOSFET, but the source and drain regions are now entirely replaced by metals. By using abrupt metal/silicon Schottky junctions, short-channel effects are avoided. Based on a few commonly used physical assumptions, we have calculated the transistor characteristics, and we find that this new three-terminal transistor can offer gain and impedance isolation, desirable for logic circuit applications.

Three mechanisms determining short-channel effects in fully-depleted SOI MOSFETs

Abstract: Mechanisms determining short-channel effects (SCE) in fully-depleted (FD) SOI MOSFETs are clarified based on experimental results of threshold voltage (V/sub T/) dependence upon gate length, and analysis using a two-dimensional (2-D) device simulator. Drain-induced barrier lowering (DIBL) effect is a well known mechanism which determines the SCE in conventional bulk MOSFETs. In FDMOSFETs, two more peculiar and important mechanisms are found out, i.e., the accumulation of majority carriers in the body region generated by impact ionization, and the DIBL effect on the barrier height for majority carriers at the edge of the source near the bottom of the body. Due to these peculiar mechanisms, V/sub T/ dependence upon gate length in the short-channel region is weakened. It is also shown that floating body effects, the scatter of V/sub T/, and transient phenomena are suppressed due to the SCE peculiar to FD MOSFETs.

A simple model for threshold voltage of surrounding-gate MOSFET's

Abstract: We propose a threshold voltage model for surrounding-gate MOSFETs. The model treats the ends and the double-gate regions of the channel as separate devices operating in parallel. The threshold voltage for the full device is obtained as the perimeter-weighted sum of the threshold voltages of the two parts enabling simple analytic threshold models to be used. Short channel effects and drain-induced barrier lowering are also modeled in this manner.

A unified model for the self-limiting hot-carrier degradation in LDD n-MOSFETs

Abstract: A new insight into the self-limiting hot-carrier degradation in lightly-doped drain (LDD) n-MOSFETs is presented. The proposed model is based on the charge pumping (CP) measurement. By progressively lowering the gate base level, the channel accumulation layer is caused to advance into the LDD gate-drain overlap and spacer oxide regions, extending the interface that can be probed. This forms the basis of a novel technique, that allows the contributions to the CP current, due to stress-induced interface states in the respective regions, to be effectively separated. Results show that interface state generation initiates in the spacer oxide region and progresses rapidly into the overlap/channel region with stress time. The close correspondence between the linear drain current degradation, measured at high and low gate bias, and the respective interface state generation in the spacer and the overlap/channel regions deduced from CP data, provides an unambiguous experimental evidence that the degradation proceeds in a two-stage mechanism, involving first a series resistance increase and saturation, followed by a carrier mobility reduction. The saturation in series resistance increase results directly from a reduced interface state generation rate in the spacer oxide. For a given density of defect precursors and considering an almost constant channel field distribution near the drain region during stress, interface trap generation rate is shown to exhibit an exponential stress time dependence, with a characteristic time constant determined by the applied voltages. This observation leads to a lifetime extrapolation methodology. Lifetime due to a particular stress drain voltage V/sub d/, may be extracted from a single composite degradation characteristic, obtained by shifting characteristics for various stress V/sub d/'s, along the stress time axis, until the characteristics merge into a single curve.

An analytical surrounding gate MOSFET model

Abstract: In this paper we present a complete and analytical drain current model for surrounding gate MOSFETs. The model was developed using a quasi-two-dimensional cylindrical form of the Poisson equation and based on the drift-diffusion equation. The model applicable for digital/analog circuit simulation contains the following advanced features: precise description of the subthreshold, near threshold and above-threshold regions of operation by one single expression; single-piece drain current equation smoothly continuous from the linear region to the saturation region; considering the source/drain resistance; inclusion of important short channel effects such as velocity saturation, drain-induced barrier lowering and channel length modulation.

Transistor operation of 30-nm gate-length EJ-MOSFETs

Abstract: We have fabricated electrically variable shallow junction metal-oxide-silicon field-effect transistors (EJ-MOSFET's) to investigate transistor characteristics of ultrafine-gate MOSFET's. By using EB direct writing onto an ultrahigh-resolution negative resist (calixarene), we achieved a gate length of 32 nm for the first time. The short-channel effects were effectively suppressed by electrically induced ultrashallow source/drain regions, and the fabricated device exhibited normal transistor characteristics even in the 32-nm gate-length regime at room temperature: an ON/OFF current ratio of 10/sup 5/ and a cut-off current of 20 pA//spl mu/m.

Epitaxial channel vertical MOS transistor

Abstract: A vertical MOS transistor includes an epitaxially formed channel between its lower source/drain region and upper source/drain region, with a gate electrode in a trench that extends vertically through those regions A process for forming the vertical MOS transistor implants the substrate to provide the lower source/drain region, then forms an epitaxial layer that provides the channel over the previously formed lower source/drain region Then, the upper source/drain region is implanted above the lower source/drain region and epitaxial channel layer, followed by formation of a vertical trench and polysilicon gate Forming the epitaxial layer over a previously implanted lower source/drain region allows independent control of the resistivity of the lower source/drain region, such that it can have low resistivity, facilitating device symmetry Also, the epitaxial channel layer has improved doping uniformity over diffusion type channel region, lowering channel length and increasing performance and yield Finally, the source/drain regions may incorporate two separate dopants to provide an extended region that further minimizes the channel length while providing higher punch through voltage levels and retaining low resistivity

Asymmetric MOS channel structure with drain extension and method for same

Abstract: A method of forming a MOS transistor without a lightly doped drain (LDD) region between the channel region and drain is provided The channel region and a drain extension are formed from two separate tilted ion implantation processes, after the deposition of the gate electrode The tilted implantation forms a relatively short channel length, with respect to the length of the gate electrode The position of the channel is offset, and directly adjoins the source A second tilted implant process forms a drain extension region under the gate electrode, adjacent the drain Elimination of LDD areas reduces the number of masking and doping steps required to manufacture a transistor Further, the drain extension area promotes transistor performance, by eliminating source resistance At the same time, sufficient doping of the drain extension area insures that the drain resistance through the drain extension remains low This drain extension acts to more evenly distribute electric fields so that large breakdown voltages are possible In this manner, larger I d currents and faster switching speeds are obtained A MOS transistor having a short, offset channel and drain extension formed through dual tilted ion implants is also provided

Method of fabricating an asymmetric channel doped MOS structure

Abstract: A method of forming a MOS transistor without a lightly doped drain (LDD) region between the channel region and drain is provided. The channel region is formed from a tilted ion implantation after the deposition of the gate oxide layer. The tilted implantation forms a relatively short channel length, with respect to the length of the gate electrode. The position of the channel is offset, and directly adjoins the source. The non-channel area under the gate, adjacent the drain, replaces the LDD region between the channel and the drain. This drain extension acts to more evenly distribute electric fields so that large breakdown voltages are possible. The small channel length, and eliminated LDD region adjacent the source, act to reduce resistance between the source and drain. In this manner, larger Id currents and faster switching speeds are obtained. A MOS transistor having a short, offset channel and drain extension is also provided.

Straddle-gate transistor: changing MOSFET channel length between off- and on-state towards achieving tunneling-defined limit of field-effect

Abstract: Some of the well-recognized constraints in the scaling of the MOSFET are: (a) random-dopants that lead to a large variance in threshold voltage, (b) oxide tunneling that leads to an increase in gate current, and hence strand-by power as well as a reduction in reliability through the increase in carrier flux, (c) limits to the magnitude and shallowness of doping that can be achieved in the source and the drain regions and that lead to poorer sub-threshold swing and higher conductance through electrostatics. The objective of this work is to point out that (a) removal of random dopant effects through removal of channel doping leaves a variance in threshold voltage that is related to lateral fluctuations in the contact region, (b) constant stand-by power density scaling leads to a constraint of 1.5-2.0 nm in oxide thickness for the gate, and (c) the shallow doping regions can be effectively replaced by inversion regions. The straddle-gate transistor, a pentode-like structure, incorporates these ideas together with that of a back-plane structure to achieve an /spl sim/10 nm length scale, where field-effect still dominates, and where the fundamental constraint of source-to-drain tunneling through silicon is restrained by modulating the effective channel length of the device between the on-state and the off-state. At least theoretically, it achieves this length scale within the constraints of power and density, but at the expense of smaller speed improvements with scaling.

Channel length independent subthreshold characteristics in submicron MOSFETs

Abstract: This work reports an anomalous subthreshold characteristic of the MOSFET for the first time. It is observed that the subthreshold characteristic does not change as the channel length decreases. The cause of channel length independent subthreshold characteristics is identified as the localized pileup of channel dopants near the source and drain ends of the channel. The low surface potential of this pileup region limits the subthreshold current of MOSFET. As a result, the ratio of on-current to off-current for this MOSFET increases as the channel length is reduced, which is an important parameter for low-voltage operation. It is found that a MOSFET with channel length independent subthreshold characteristic is more suitable for low-voltage operation.

Nonscaling of MOSFET's linear resistance in the deep submicrometer regime

Abstract: This paper investigates the scaling properties of deep submicron MOSFET's and shows that, while in a wide range of channel lengths they can be represented as composed by a scaling intrinsic and a nonscaling parasitic part, this picture does no longer hold for shorter transistors. A nonscaling of the total resistance R/sub TOT/=[V/sub DS//I/sub DS/] of short devices is observed, and its impact on parasitic resistances and effective channel length extraction is discussed. A possible explanation is suggested in relation to the two-dimensional substrate doping redistribution linked to reverse-short-channel effects.

Depleted poly-silicon edged MOSFET structure and method

Abstract: A field effect transistor with reduced corner device problems comprises source and drain regions formed in a substrate, a channel region between the source and drain regions, isolation regions in the substrate adjacent the source, channel and drain regions; and a gate having a gate dopant over the channel region and separated therefrom by a gate dielectric. The isolation regions define corner regions of the channel along interfaces between the channel and isolation regions. The gate includes regions depleted of the gate dopant and overlapping at least the channel region and the isolation regions, such that voltage thresholds of the channel corner regions beneath depleted portions of the gate conductor layer are increased compared to regions of the channel between the corner regions. The field effect transistor with reduced dopant concentration on the MOSFET gate "corner" has an improved edge voltage tolerance. The structure has improved edge dielectric breakdown and lower MOSFET gate-induced drain leakage (GIDL). This structure is intended for analog applications, mixed voltage tolerant circuits and electrostatic (ESD) networks.

Novel low capacitance sidewall elevated drain dynamic threshold voltage MOSFET (LCSED) for ultra low power dual gate CMOS technology

Abstract: We have developed a novel high speed dynamic threshold voltage MOSFET named LCSED for ultra low power operation This was realized using sidewall elevated drain The LCSED achieved the following excellent characteristics as compared to the bulk-DTMOS which we proposed earlier: 60% reduced occupation area; 65% reduced junction capacitance; 67% reduced forward leakage current between shallow-well and source/drain; lower transistor series resistance; smaller short channel effect; higher drive current These effects realize ultra low power high speed operation

A compact LDD MOSFET I-V model based on nonpinned surface potential

Abstract: Based on nonpinned surface potential concept, in this paper we present a compact single-piece and complete I-V model for submicron lightly-doped drain (LDD) MOSFETs. The physics-based and analytical model was developed using the drift-diffusion equation and based on the quasi two-dimensional (2-D) Poisson equation. The important short-channel device features: drain-induced-barrier-lowering (DIBL), channel-length modulation (CLM), velocity saturation, and the parasitic series source and drain resistances have been included in the model in a physically consistent manner. In this model, the LDD region is treated as a bias-dependent series resistance, and the drain-voltage drop across the LDD region has been considered in modeling the DIBL effect. This model is smoothly-continuous, valid in all regions of operation and suitable for efficient circuit simulation. The accuracy of the model has been checked by comparing the calculated drain current, conductance and transconductance with the experimental data.

A DC model for asymmetric trapezoidal gate MOSFET's in strong inversion

Abstract: Asymmetric trapezoidal gate (ATG) MOSFET is an innovative device having a structure of a relatively narrow drain-side width in order to reduce parasitic effects for enhancing device performance. In this paper, we develop a DC model for ATG MOSFET's. We use a charge-based approach to explore the asymmetric feature between source and drain of ATG MOSFET's, and obtain analytic formulae for threshold voltage, body effect, drain current, and channel length modulation effect in linear and saturation regions for both forward and reverse modes of operations. The model provides a physical analysis of the ATG structure, shows good agreement with measurement data, and is useful in circuit simulation with ATG devices.

A single-piece charge-based model for the output conductance of MOS transistors

Abstract: This paper presents a physically based model of the MOSFET output conductance. The drain current and the output conductance of the MOS transistor are accurately described by single-piece functions of the inversion charge densities at source and drain. Carrier velocity saturation, channel length modulation (CLM) and drain induced barrier lowering (DIBL) are included in a single-piece analytical model. The results can be readily applied for first order analog circuit hand calculation.

Precision improvement in current-mode winner-take-all circuits using gain-boosted regulated-cascode CMOS stages

Abstract: This paper presents a study on advantages and concerns of using gain-boosted regulated-cascoding technique in current-mode winner-take-all (WTA) circuits. For large scale integration and high frequency applications the use of MOS transistors with minimum feature size is a must. However, modern MOS transistors with sub-micron channel length exhibit pronounced channel-length modulation. This deficiency causes precision degradation in WTA circuits. With the use of gain-boosted regulated cascoding technique, a very high precision can be achieved in current-mode WTA circuits formed using sub-micrometer transistors.

A new SOI MOSFET for low power applications

Abstract: SOI devices have attracted a great deal of interest due to their inherent advantages for low power and high performance applications. Assaderaghi et al. proposed the DTMOS (dynamic threshold-voltage MOSFET) for ultra-low voltage VLSI applications (1997). Several researchers proposed a modified SOI MOSFET with the channel body connected to the drain through a small auxiliary MOSFET (Chung et al. 1996; Houston, 1997) to increase the operating voltage. In this paper, we propose a new SOI MOSFET with an auxiliary MOSFET in which the gate and drain are shorted to the gate of the main transistor and the source is connected to the channel body of the main transistor. This auxiliary transistor applies a positive bias to the channel body of the main transistor. In this paper, we present some experimental data and compare the proposed device with a conventional MOSFET, a DTMOS, and the modified SOI MOSFET proposed by Chung et al.

Pseudo-SOI: P-N-P-channel-doped bulk MOSFET for low-voltage high-performance applications

Abstract: A "pseudo-SOI (P-SOI)" MOSFET using a bulk substrate with small subthreshold swing, high drain current, low junction capacitance, and low substrate-bias coefficient comparable to those of thin-film SOI MOSFET has been developed. The P-SOI MOSFET features a P-N-P channel profile, in which the sandwiched N-type layer is fully depleted by the internal built-in potential. Fabricated 0.25-/spl mu/m P-SOI MOSFET achieves subthreshold swing of 73 mV/decade and had a 25% larger drain current, 60% lower source/drain junction capacitance, and 40% lower substrate-bias coefficient than those of a control MOSFET.

High withstand voltage ic

Abstract: PROBLEM TO BE SOLVED: To increase N-channel and P-channel level shifters in parasitic resistance SOLUTION: An opening 21 is provided in an N well region 1 to make a P-substrate 100 locally exposed, where the N well region 1 is located between an N drain region 5 and an N region 3 of a high-withstand voltage N-channel MOSFET, and an opening 22 is provided in P offset region 2 to make an N well region exposed to form a high-resistance region, where the P offset region 2 is located between the P drain region 18 and a P well region 4 of a high-withstand voltage P channel MOSFET With this setup, a parasitic resistance present between an N region or a P region connected to a power supply and a drain region can be increase, without deteriorating both the high-withstand voltage N-channel MOSFET of an N channel level shifter and the high-withstand voltage P channel MOSFET of a P channel level shifter in withstand voltage characteristics

Synchronous rectifier MOFSET with controlled channel voltage drop

Abstract: A synchronous rectifier MOSFET control circuit which overcomes many of the shortcomings of the prior art employs MOSFET for supplying voltage to a load when the MOSFET is in the forward biased condition (i.e., when an input voltage level exceeds the threshold voltage level by a pre-determined amount). The MOSFET control circuit is configured to turn off the MOSFET when the input voltage level dips below that pre-determined level required to maintain the MOSFET in the forward biased condition. When the MOSFET is turned off, the diode internal to the MOSFET device prevents current flow in the reverse bias direction (i.e., the internal diode prevents current flow from the output to the input), effectively isolating the load from the input voltage source, thereby allowing the capacitors to discharge their energy to the load to maintain a voltage supply to the load which is at or above the output load threshold voltage level. Thus, although a diode is still employed to prevent current flow in the reverse direction, the diode need not function to supply the current to the load when the MOSFET is in the forward biased direction. Rather, current flows through the MOSFET channel (as opposed to flowing through the diode) when the MOSFET is in the forward biased condition.

A compact pre- and post-stress I-V model for submicrometer buried-channel pMOSFETs

Abstract: In this paper, we report a new complete and analytical drain current model for pre- and post-stress submicrometer buried-channel (BC) MOSFETs operated in the forward- and reverse-biased modes. The model is valid in all regions of operation, and is developed using the quasi-two-dimensional approach. The hot-carrier-induced electron trapping in the oxide causes the channel shortening effect, which displays different behaviors for the device operated in the forward and reverse modes. It affects the threshold voltage reduction with channel length. This model incorporates the effects of velocity saturation, drain induced barrier lowering, channel length modulation, gate voltage induced mobility degradation, series source and drain resistances, and hot-carrier-induced oxide charges. The damaged channel region due to the fixed oxide charges trapped during hot-carrier injection is treated as a bias- and stress-time-dependent resistance. The resulting degraded BC MOSFET model is applicable for circuit simulation and its accuracy has been checked by the experimental data.

Deep-Submicron Lightly-Doped-Drain and Single-Drain Metal-Oxide-Semiconductor Transistor Drain Current Model for Circuit Simulation

Abstract: A new deep submicron I–V model for lightly-doped drain (LDD) and single-drain (SD) metal-oxide-semiconductor-field-effect-transistors (MOSFET) is presented. The physics-based and analytical model is developed using the drift-diffusion equation with a modified mobility formula to consider the effect of velocity overshoot and based on the quasi-two-dimensional Poisson equation. The drain-induced-barrier-lowering (DIBL), channel-length modulation, velocity overshoot, and parasitic source and drain resistances have been included in the model in a physically consistent manner. In this model, the LDD region is treated as a bias-dependent series resistance, and the drain-voltage drop across the LDD region has been considered in modeling the DIBL effect. This model is smoothly-continuous and valid in all regions of operation, its accuracy has been checked by comparing the calculated drain current, conductance and transconductance with the experimental data.

Noise reduction method for a semiconductor device

Abstract: A 1 /f noise coefficient characteristic with respect to an operating point of a semiconductor device is measured, and a control voltage corresponding to an operating point of the semiconductor device with which the 1 /f noise coefficient is minimized is applied to a MOSFET. Further, using a MOSFET which has known element dimensions, a relationship of a 1 /f noise coefficient to a channel area is calculated, and the resistance value of the MOSFET is calculated using the channel width and the channel length as well as a constant peculiar to the MOSFET. Then, the 1 /f noise coefficient of the semiconductor device is calculated using the 1 /f noise coefficient with respect to the channel area of the MOSFET and the resistance value, and the channel width and the channel length of the MOSFET are set so that the 1 /f noise coefficient of the semiconductor device may be minimized.

A simple DC model for dual channel high electron mobility transistors

Abstract: In this paper, a DC model for the dual channel high electron mobility transistor (DC-HEMT) is presented. The model is developed based on a single charge expression that describes four different charge components: two dimensional electron gas on the top and bottom channels, free electrons and the neutralized donors in the AlGaAs layer. This expression not only shows the smoothness of the charges over a wide range of applied gate voltages but also shows a good agreement with the numerical solution of the charges. The current-voltage characteristics are derived including the effect of the parasitic source and drain resistances, the mobility degradation and channel length modulation through a quasi two dimensional Poisson equation in the high field region of the channel. Finally, the theoretical predictions of the model are compared with the experimental data and found to be in good agreement.

Effect of deep-level impurities on the drain characteristics of short-channel metal-semiconductor field effect transistors

Abstract: The role of deep-level impurities in the drain characteristics of a short-channel metal-semiconductor field effect transistor has been investigated. The drain current of the device has been evaluated for different values of deep-level density and at different temperatures ranging from 300 to 400 K. The presence of deep levels gives rise to an excess drain current resulting from the electronic excitations from the defect levels. The increase in the temperature enhances the current due to increasing ionization of the defects. An analytical expression for the channel conductance is also derived and it is found to be a function of deep-level concentration besides other nonidealities such as interface states and interfacial oxide layer. The effect of gate length shortening also reveals significant changes in the current and conductance.